dd78b0c7e895147a2745153aab0ab58ab888797a
[platform/kernel/u-boot.git] / include / configs / cm_t3517.h
1 /*
2  * (C) Copyright 2013 CompuLab, Ltd.
3  * Author: Igor Grinberg <grinberg@compulab.co.il>
4  *
5  * Configuration settings for the CompuLab CM-T3517 board
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_CM_T3517 /* working with CM-T3517 */
17
18 #define CONFIG_SYS_TEXT_BASE    0x80008000
19
20 /*
21  * This is needed for the DMA stuff.
22  * Although the default iss 64, we still define it
23  * to be on the safe side once the default is changed.
24  */
25
26 #define CONFIG_EMIF4    /* The chip has EMIF4 controller */
27
28 #include <asm/arch/cpu.h>               /* get chip and board defs */
29 #include <asm/arch/omap.h>
30
31 #define CONFIG_MACH_TYPE                MACH_TYPE_CM_T3517
32
33 /* Clock Defines */
34 #define V_OSCK                  26000000        /* Clock output from T2 */
35 #define V_SCLK                  (V_OSCK >> 1)
36
37 #define CONFIG_MISC_INIT_R
38
39 /*
40  * The early kernel mapping on ARM currently only maps from the base of DRAM
41  * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
42  * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
43  * so that leaves DRAM base to DRAM base + 0x4000 available.
44  */
45 #define CONFIG_SYS_BOOTMAPSZ            0x4000
46
47 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
48 #define CONFIG_SETUP_MEMORY_TAGS
49 #define CONFIG_INITRD_TAG
50 #define CONFIG_REVISION_TAG
51 #define CONFIG_SERIAL_TAG
52
53 /*
54  * Size of malloc() pool
55  */
56 #define CONFIG_ENV_SIZE         (128 << 10)     /* 128 KiB */
57 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
58
59 /*
60  * Hardware drivers
61  */
62
63 /*
64  * NS16550 Configuration
65  */
66 #define CONFIG_SYS_NS16550_SERIAL
67 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
68 #define CONFIG_SYS_NS16550_CLK          48000000        /* 48MHz (APLL96/2) */
69
70 /*
71  * select serial console configuration
72  */
73 #define CONFIG_CONS_INDEX               3
74 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
75 #define CONFIG_SERIAL3                  3       /* UART3 */
76
77 /* allow to overwrite serial and ethaddr */
78 #define CONFIG_ENV_OVERWRITE
79 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
80                                         115200}
81
82 /* USB */
83 #define CONFIG_USB_MUSB_AM35X
84
85 #ifndef CONFIG_USB_MUSB_AM35X
86 #define CONFIG_USB_OMAP3
87 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
88 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
89 #else /* !CONFIG_USB_MUSB_AM35X */
90 #define CONFIG_USB_MUSB_PIO_ONLY
91 #endif /* CONFIG_USB_MUSB_AM35X */
92
93 /* commands to include */
94 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
95 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
96 #define CONFIG_MTD_PARTITIONS
97 #define MTDIDS_DEFAULT          "nand0=nand"
98 #define MTDPARTS_DEFAULT        "mtdparts=nand:512k(x-loader),"\
99                                 "1920k(u-boot),256k(u-boot-env),"\
100                                 "4m(kernel),-(fs)"
101
102 #define CONFIG_CMD_NAND         /* NAND support                 */
103
104 #define CONFIG_SYS_I2C
105 #define CONFIG_SYS_OMAP24_I2C_SPEED     400000
106 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
107 #define CONFIG_SYS_I2C_OMAP34XX
108 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
109 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
110 #define CONFIG_SYS_I2C_EEPROM_BUS       0
111 #define CONFIG_I2C_MULTI_BUS
112
113 /*
114  * Board NAND Info.
115  */
116 #define CONFIG_NAND_OMAP_GPMC
117 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
118                                                         /* to access nand */
119 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
120                                                         /* to access nand at */
121                                                         /* CS0 */
122 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
123                                                         /* devices */
124
125 /* Environment information */
126 #define CONFIG_EXTRA_ENV_SETTINGS \
127         "loadaddr=0x82000000\0" \
128         "baudrate=115200\0" \
129         "console=ttyO2,115200n8\0" \
130         "netretry=yes\0" \
131         "mpurate=auto\0" \
132         "vram=12M\0" \
133         "dvimode=1024x768MR-16@60\0" \
134         "defaultdisplay=dvi\0" \
135         "mmcdev=0\0" \
136         "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
137         "mmcrootfstype=ext4\0" \
138         "nandroot=/dev/mtdblock4 rw\0" \
139         "nandrootfstype=ubifs\0" \
140         "mmcargs=setenv bootargs console=${console} " \
141                 "mpurate=${mpurate} " \
142                 "vram=${vram} " \
143                 "omapfb.mode=dvi:${dvimode} " \
144                 "omapdss.def_disp=${defaultdisplay} " \
145                 "root=${mmcroot} " \
146                 "rootfstype=${mmcrootfstype}\0" \
147         "nandargs=setenv bootargs console=${console} " \
148                 "mpurate=${mpurate} " \
149                 "vram=${vram} " \
150                 "omapfb.mode=dvi:${dvimode} " \
151                 "omapdss.def_disp=${defaultdisplay} " \
152                 "root=${nandroot} " \
153                 "rootfstype=${nandrootfstype}\0" \
154         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
155         "bootscript=echo Running bootscript from mmc ...; " \
156                 "source ${loadaddr}\0" \
157         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
158         "mmcboot=echo Booting from mmc ...; " \
159                 "run mmcargs; " \
160                 "bootm ${loadaddr}\0" \
161         "nandboot=echo Booting from nand ...; " \
162                 "run nandargs; " \
163                 "nand read ${loadaddr} 2a0000 400000; " \
164                 "bootm ${loadaddr}\0" \
165
166 #define CONFIG_BOOTCOMMAND \
167         "mmc dev ${mmcdev}; if mmc rescan; then " \
168                 "if run loadbootscript; then " \
169                         "run bootscript; " \
170                 "else " \
171                         "if run loaduimage; then " \
172                                 "run mmcboot; " \
173                         "else run nandboot; " \
174                         "fi; " \
175                 "fi; " \
176         "else run nandboot; fi"
177
178 /*
179  * Miscellaneous configurable options
180  */
181 #define CONFIG_AUTO_COMPLETE
182 #define CONFIG_CMDLINE_EDITING
183 #define CONFIG_TIMESTAMP
184 #define CONFIG_SYS_AUTOLOAD             "no"
185 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
186 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
187 /* Print Buffer Size */
188 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
189                                         sizeof(CONFIG_SYS_PROMPT) + 16)
190 #define CONFIG_SYS_MAXARGS              32      /* max number of command args */
191 /* Boot Argument Buffer Size */
192 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
193
194 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
195
196 /*
197  * AM3517 has 12 GP timers, they can be driven by the system clock
198  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
199  * This rate is divided by a local divisor.
200  */
201 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
202 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
203 #define CONFIG_SYS_HZ                   1000
204
205 /*-----------------------------------------------------------------------
206  * Physical Memory Map
207  */
208 #define CONFIG_NR_DRAM_BANKS    1       /* CM-T3517 DRAM is only on CS0 */
209 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
210 #define CONFIG_SYS_CS0_SIZE             (256 << 20)
211
212 /*-----------------------------------------------------------------------
213  * FLASH and environment organization
214  */
215
216 /* **** PISMO SUPPORT *** */
217 /* Monitor at start of flash */
218 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
219 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
220
221 #define CONFIG_ENV_IS_IN_NAND
222 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
223 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
224 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
225
226 #if defined(CONFIG_CMD_NET)
227 #define CONFIG_DRIVER_TI_EMAC
228 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
229 #define CONFIG_MII
230 #define CONFIG_SMC911X
231 #define CONFIG_SMC911X_32_BIT
232 #define CONFIG_SMC911X_BASE     (0x2C000000 + (16 << 20))
233 #define CONFIG_ARP_TIMEOUT              200UL
234 #define CONFIG_NET_RETRY_COUNT          5
235 #endif /* CONFIG_CMD_NET */
236
237 /* additions for new relocation code, must be added to all boards */
238 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
239 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
240 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
241 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
242                                          CONFIG_SYS_INIT_RAM_SIZE -     \
243                                          GENERATED_GBL_DATA_SIZE)
244
245 /* Status LED */
246 #define GREEN_LED_GPIO                  186 /* CM-T3517 Green LED is GPIO186 */
247
248 /* Display Configuration */
249 #define CONFIG_VIDEO_OMAP3
250 #define LCD_BPP         LCD_COLOR16
251
252 #define CONFIG_SPLASH_SCREEN
253 #define CONFIG_SPLASHIMAGE_GUARD
254 #define CONFIG_BMP_16BPP
255 #define CONFIG_SCF0403_LCD
256
257 #define CONFIG_OMAP3_SPI
258
259 /* EEPROM */
260 #define CONFIG_ENV_EEPROM_IS_ON_I2C
261 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
262 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
263 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
264 #define CONFIG_SYS_EEPROM_SIZE                  256
265
266 #endif /* __CONFIG_H */