include/configs/cm_t35.h

   1 /*
   2  * (C) Copyright 2011 CompuLab, Ltd.
   3  * Mike Rapoport <mike@compulab.co.il>
   4  * Igor Grinberg <grinberg@compulab.co.il>
   5  *
   6  * Based on omap3_beagle.h
   7  * (C) Copyright 2006-2008
   8  * Texas Instruments.
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  * Syed Mohammed Khasim <x0khasim@ti.com>
  11  *
  12  * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 #define CONFIG_SYS_CACHELINE_SIZE       64
  21
  22 /*
  23  * High Level Configuration Options
  24  */
  25 #define CONFIG_OMAP_GPIO
  26 #define CONFIG_CM_T3X   /* working with CM-T35 and CM-T3730 */
  27
  28 #define CONFIG_SDRC     /* The chip has SDRC controller */
  29
  30 #include <asm/arch/cpu.h>               /* get chip and board defs */
  31 #include <asm/arch/omap.h>
  32
  33 /* Clock Defines */
  34 #define V_OSCK                  26000000        /* Clock output from T2 */
  35 #define V_SCLK                  (V_OSCK >> 1)
  36
  37 #define CONFIG_MISC_INIT_R
  38
  39 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  40 #define CONFIG_SETUP_MEMORY_TAGS
  41 #define CONFIG_INITRD_TAG
  42 #define CONFIG_REVISION_TAG
  43 #define CONFIG_SERIAL_TAG
  44
  45 /*
  46  * Size of malloc() pool
  47  */
  48 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
  49                                         /* Sector */
  50 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  51
  52 /*
  53  * Hardware drivers
  54  */
  55
  56 /*
  57  * NS16550 Configuration
  58  */
  59 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  60
  61 #define CONFIG_SYS_NS16550_SERIAL
  62 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  63 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  64
  65 /*
  66  * select serial console configuration
  67  */
  68 #define CONFIG_CONS_INDEX               3
  69 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  70 #define CONFIG_SERIAL3                  3       /* UART3 */
  71
  72 /* allow to overwrite serial and ethaddr */
  73 #define CONFIG_ENV_OVERWRITE
  74 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  75                                         115200}
  76
  77 /* USB */
  78 #define CONFIG_USB_OMAP3
  79 #define CONFIG_USB_EHCI
  80 #define CONFIG_USB_EHCI_OMAP
  81 #define CONFIG_USB_MUSB_UDC
  82 #define CONFIG_TWL4030_USB
  83
  84 /* USB device configuration */
  85 #define CONFIG_USB_DEVICE
  86 #define CONFIG_USB_TTY
  87
  88 /* commands to include */
  89 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
  90 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  91 #define CONFIG_MTD_PARTITIONS
  92 #define MTDIDS_DEFAULT          "nand0=nand"
  93 #define MTDPARTS_DEFAULT        "mtdparts=nand:512k(x-loader),"\
  94                                 "1920k(u-boot),256k(u-boot-env),"\
  95                                 "4m(kernel),-(fs)"
  96
  97 #define CONFIG_CMD_NAND         /* NAND support                 */
  98
  99 #define CONFIG_SYS_I2C
 100 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 101 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 102 #define CONFIG_SYS_I2C_OMAP34XX
 103 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 104 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 105 #define CONFIG_SYS_I2C_EEPROM_BUS       0
 106 #define CONFIG_I2C_MULTI_BUS
 107
 108 /*
 109  * TWL4030
 110  */
 111 #define CONFIG_TWL4030_LED
 112
 113 /*
 114  * Board NAND Info.
 115  */
 116 #define CONFIG_NAND_OMAP_GPMC
 117 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 118                                                         /* to access nand */
 119 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 120                                                         /* to access nand at */
 121                                                         /* CS0 */
 122 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 123                                                         /* devices */
 124
 125 /* Environment information */
 126 #define CONFIG_EXTRA_ENV_SETTINGS \
 127         "loadaddr=0x82000000\0" \
 128         "usbtty=cdc_acm\0" \
 129         "console=ttyO2,115200n8\0" \
 130         "mpurate=500\0" \
 131         "vram=12M\0" \
 132         "dvimode=1024x768MR-16@60\0" \
 133         "defaultdisplay=dvi\0" \
 134         "mmcdev=0\0" \
 135         "mmcroot=/dev/mmcblk0p2 rw\0" \
 136         "mmcrootfstype=ext4 rootwait\0" \
 137         "nandroot=/dev/mtdblock4 rw\0" \
 138         "nandrootfstype=ubifs\0" \
 139         "mmcargs=setenv bootargs console=${console} " \
 140                 "mpurate=${mpurate} " \
 141                 "vram=${vram} " \
 142                 "omapfb.mode=dvi:${dvimode} " \
 143                 "omapdss.def_disp=${defaultdisplay} " \
 144                 "root=${mmcroot} " \
 145                 "rootfstype=${mmcrootfstype}\0" \
 146         "nandargs=setenv bootargs console=${console} " \
 147                 "mpurate=${mpurate} " \
 148                 "vram=${vram} " \
 149                 "omapfb.mode=dvi:${dvimode} " \
 150                 "omapdss.def_disp=${defaultdisplay} " \
 151                 "root=${nandroot} " \
 152                 "rootfstype=${nandrootfstype}\0" \
 153         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 154         "bootscript=echo Running bootscript from mmc ...; " \
 155                 "source ${loadaddr}\0" \
 156         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 157         "mmcboot=echo Booting from mmc ...; " \
 158                 "run mmcargs; " \
 159                 "bootm ${loadaddr}\0" \
 160         "nandboot=echo Booting from nand ...; " \
 161                 "run nandargs; " \
 162                 "nand read ${loadaddr} 2a0000 400000; " \
 163                 "bootm ${loadaddr}\0" \
 164
 165 #define CONFIG_BOOTCOMMAND \
 166         "mmc dev ${mmcdev}; if mmc rescan; then " \
 167                 "if run loadbootscript; then " \
 168                         "run bootscript; " \
 169                 "else " \
 170                         "if run loaduimage; then " \
 171                                 "run mmcboot; " \
 172                         "else run nandboot; " \
 173                         "fi; " \
 174                 "fi; " \
 175         "else run nandboot; fi"
 176
 177 /*
 178  * Miscellaneous configurable options
 179  */
 180 #define CONFIG_AUTO_COMPLETE
 181 #define CONFIG_CMDLINE_EDITING
 182 #define CONFIG_TIMESTAMP
 183 #define CONFIG_SYS_AUTOLOAD             "no"
 184 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 185 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 186 /* Print Buffer Size */
 187 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 188                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 189 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 190 /* Boot Argument Buffer Size */
 191 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 192
 193 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 194                                                                 /* works on */
 195 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 196                                         0x01F00000) /* 31MB */
 197
 198 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 199                                                         /* load address */
 200
 201 /*
 202  * OMAP3 has 12 GP timers, they can be driven by the system clock
 203  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 204  * This rate is divided by a local divisor.
 205  */
 206 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 207 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 208
 209 /*-----------------------------------------------------------------------
 210  * Physical Memory Map
 211  */
 212 #define CONFIG_NR_DRAM_BANKS    1       /* CS1 is never populated */
 213 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 214
 215 /*-----------------------------------------------------------------------
 216  * FLASH and environment organization
 217  */
 218
 219 /* **** PISMO SUPPORT *** */
 220 /* Monitor at start of flash */
 221 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 222 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 223
 224 #define CONFIG_ENV_IS_IN_NAND
 225 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 226 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 227 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 228
 229 #if defined(CONFIG_CMD_NET)
 230 #define CONFIG_SMC911X
 231 #define CONFIG_SMC911X_32_BIT
 232 #define CM_T3X_SMC911X_BASE     0x2C000000
 233 #define SB_T35_SMC911X_BASE     (CM_T3X_SMC911X_BASE + (16 << 20))
 234 #define CONFIG_SMC911X_BASE     CM_T3X_SMC911X_BASE
 235 #endif /* (CONFIG_CMD_NET) */
 236
 237 /* additions for new relocation code, must be added to all boards */
 238 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 239 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 240 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 241 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 242                                          CONFIG_SYS_INIT_RAM_SIZE -     \
 243                                          GENERATED_GBL_DATA_SIZE)
 244
 245 /* Status LED */
 246 #define GREEN_LED_GPIO                  186 /* CM-T35 Green LED is GPIO186 */
 247
 248 #define CONFIG_SPLASHIMAGE_GUARD
 249
 250 /* GPIO banks */
 251 #ifdef CONFIG_LED_STATUS
 252 #define CONFIG_OMAP3_GPIO_6     /* GPIO186 is in GPIO bank 6  */
 253 #endif
 254
 255 /* Display Configuration */
 256 #define CONFIG_OMAP3_GPIO_2
 257 #define CONFIG_OMAP3_GPIO_5
 258 #define CONFIG_VIDEO_OMAP3
 259 #define LCD_BPP         LCD_COLOR16
 260
 261 #define CONFIG_SPLASH_SCREEN
 262 #define CONFIG_SPLASH_SOURCE
 263 #define CONFIG_BMP_16BPP
 264 #define CONFIG_SCF0403_LCD
 265
 266 #define CONFIG_OMAP3_SPI
 267
 268 /* Defines for SPL */
 269 #define CONFIG_SPL_FRAMEWORK
 270 #define CONFIG_SPL_NAND_SIMPLE
 271
 272 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 273 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 274
 275 #define CONFIG_SPL_BOARD_INIT
 276 #define CONFIG_SPL_NAND_BASE
 277 #define CONFIG_SPL_NAND_DRIVERS
 278 #define CONFIG_SPL_NAND_ECC
 279 #define CONFIG_SPL_OMAP3_ID_NAND
 280 #define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 281
 282 /* NAND boot config */
 283 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 284 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 285 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 286 #define CONFIG_SYS_NAND_OOBSIZE         64
 287 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 288 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 289 /*
 290  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 291  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 292  */
 293 #define CONFIG_SYS_NAND_ECCPOS          { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
 294                                          10, 11, 12 }
 295 #define CONFIG_SYS_NAND_ECCSIZE         512
 296 #define CONFIG_SYS_NAND_ECCBYTES        3
 297 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 298
 299 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 300 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 301
 302 #define CONFIG_SPL_TEXT_BASE            0x40200800
 303 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 304                                          CONFIG_SPL_TEXT_BASE)
 305
 306 /*
 307  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 308  * older x-loader implementations. And move the BSS area so that it
 309  * doesn't overlap with TEXT_BASE.
 310  */
 311 #define CONFIG_SYS_TEXT_BASE            0x80008000
 312 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 313 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 314
 315 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 316 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 317
 318 /* EEPROM */
 319 #define CONFIG_CMD_EEPROM
 320 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 321 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 322 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 323 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 324 #define CONFIG_SYS_EEPROM_SIZE                  256
 325
 326 #define CONFIG_CMD_EEPROM_LAYOUT
 327 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
 328
 329 #endif /* __CONFIG_H */