Merge branch '2019-05-24-master-imports'
[platform/kernel/u-boot.git] / include / configs / cm_t35.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2011 CompuLab, Ltd.
4  * Mike Rapoport <mike@compulab.co.il>
5  * Igor Grinberg <grinberg@compulab.co.il>
6  *
7  * Based on omap3_beagle.h
8  * (C) Copyright 2006-2008
9  * Texas Instruments.
10  * Richard Woodruff <r-woodruff2@ti.com>
11  * Syed Mohammed Khasim <x0khasim@ti.com>
12  *
13  * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
14  */
15
16 #ifndef __CONFIG_H
17 #define __CONFIG_H
18
19 #define CONFIG_SYS_CACHELINE_SIZE       64
20
21 /*
22  * High Level Configuration Options
23  */
24 #define CONFIG_CM_T3X   /* working with CM-T35 and CM-T3730 */
25
26 #include <asm/arch/cpu.h>               /* get chip and board defs */
27 #include <asm/arch/omap.h>
28
29 /* Clock Defines */
30 #define V_OSCK                  26000000        /* Clock output from T2 */
31 #define V_SCLK                  (V_OSCK >> 1)
32
33 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
34 #define CONFIG_SETUP_MEMORY_TAGS
35 #define CONFIG_INITRD_TAG
36 #define CONFIG_REVISION_TAG
37 #define CONFIG_SERIAL_TAG
38
39 /*
40  * Size of malloc() pool
41  */
42 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
43                                         /* Sector */
44 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
45
46 /*
47  * Hardware drivers
48  */
49
50 /*
51  * NS16550 Configuration
52  */
53 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
54
55 #define CONFIG_SYS_NS16550_SERIAL
56 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
57 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
58
59 /*
60  * select serial console configuration
61  */
62 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
63
64 /* allow to overwrite serial and ethaddr */
65 #define CONFIG_ENV_OVERWRITE
66 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
67                                         115200}
68
69 /* USB device configuration */
70 #define CONFIG_USB_DEVICE
71 #define CONFIG_USB_TTY
72
73 /* commands to include */
74
75 #define CONFIG_SYS_I2C
76 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
77 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
78 #define CONFIG_SYS_I2C_EEPROM_BUS       0
79 #define CONFIG_I2C_MULTI_BUS
80
81 /*
82  * TWL4030
83  */
84
85 /*
86  * Board NAND Info.
87  */
88 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
89                                                         /* to access nand at */
90                                                         /* CS0 */
91 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
92                                                         /* devices */
93
94 /* Environment information */
95 #define CONFIG_EXTRA_ENV_SETTINGS \
96         "loadaddr=0x82000000\0" \
97         "usbtty=cdc_acm\0" \
98         "console=ttyO2,115200n8\0" \
99         "mpurate=500\0" \
100         "vram=12M\0" \
101         "dvimode=1024x768MR-16@60\0" \
102         "defaultdisplay=dvi\0" \
103         "mmcdev=0\0" \
104         "mmcroot=/dev/mmcblk0p2 rw\0" \
105         "mmcrootfstype=ext4 rootwait\0" \
106         "nandroot=/dev/mtdblock4 rw\0" \
107         "nandrootfstype=ubifs\0" \
108         "mmcargs=setenv bootargs console=${console} " \
109                 "mpurate=${mpurate} " \
110                 "vram=${vram} " \
111                 "omapfb.mode=dvi:${dvimode} " \
112                 "omapdss.def_disp=${defaultdisplay} " \
113                 "root=${mmcroot} " \
114                 "rootfstype=${mmcrootfstype}\0" \
115         "nandargs=setenv bootargs console=${console} " \
116                 "mpurate=${mpurate} " \
117                 "vram=${vram} " \
118                 "omapfb.mode=dvi:${dvimode} " \
119                 "omapdss.def_disp=${defaultdisplay} " \
120                 "root=${nandroot} " \
121                 "rootfstype=${nandrootfstype}\0" \
122         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
123         "bootscript=echo Running bootscript from mmc ...; " \
124                 "source ${loadaddr}\0" \
125         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
126         "mmcboot=echo Booting from mmc ...; " \
127                 "run mmcargs; " \
128                 "bootm ${loadaddr}\0" \
129         "nandboot=echo Booting from nand ...; " \
130                 "run nandargs; " \
131                 "nand read ${loadaddr} 2a0000 400000; " \
132                 "bootm ${loadaddr}\0" \
133
134 #define CONFIG_BOOTCOMMAND \
135         "mmc dev ${mmcdev}; if mmc rescan; then " \
136                 "if run loadbootscript; then " \
137                         "run bootscript; " \
138                 "else " \
139                         "if run loaduimage; then " \
140                                 "run mmcboot; " \
141                         "else run nandboot; " \
142                         "fi; " \
143                 "fi; " \
144         "else run nandboot; fi"
145
146 /*
147  * Miscellaneous configurable options
148  */
149 #define CONFIG_TIMESTAMP
150 #define CONFIG_SYS_AUTOLOAD             "no"
151
152 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
153                                                                 /* works on */
154 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
155                                         0x01F00000) /* 31MB */
156
157 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
158                                                         /* load address */
159
160 /*
161  * OMAP3 has 12 GP timers, they can be driven by the system clock
162  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
163  * This rate is divided by a local divisor.
164  */
165 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
166 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
167
168 /*-----------------------------------------------------------------------
169  * Physical Memory Map
170  */
171 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
172
173 /*-----------------------------------------------------------------------
174  * FLASH and environment organization
175  */
176
177 /* **** PISMO SUPPORT *** */
178 /* Monitor at start of flash */
179 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
180 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
181
182 #define CONFIG_ENV_OFFSET               0x260000
183 #define CONFIG_ENV_ADDR                 0x260000
184
185 /* additions for new relocation code, must be added to all boards */
186 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
187 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
188 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
189 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
190                                          CONFIG_SYS_INIT_RAM_SIZE -     \
191                                          GENERATED_GBL_DATA_SIZE)
192
193 /* Status LED */
194 #define GREEN_LED_GPIO                  186 /* CM-T35 Green LED is GPIO186 */
195
196 #define CONFIG_SPLASHIMAGE_GUARD
197
198 /* Display Configuration */
199 #define LCD_BPP         LCD_COLOR16
200
201 #define CONFIG_SPLASH_SCREEN
202 #define CONFIG_SPLASH_SOURCE
203 #define CONFIG_BMP_16BPP
204 #define CONFIG_SCF0403_LCD
205
206 /* Defines for SPL */
207
208 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
209 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
210
211 #define CONFIG_SPL_NAND_BASE
212 #define CONFIG_SPL_NAND_DRIVERS
213 #define CONFIG_SPL_NAND_ECC
214
215 /* NAND boot config */
216 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
217 #define CONFIG_SYS_NAND_PAGE_COUNT      64
218 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
219 #define CONFIG_SYS_NAND_OOBSIZE         64
220 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
221 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
222 /*
223  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
224  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
225  */
226 #define CONFIG_SYS_NAND_ECCPOS          { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
227                                          10, 11, 12 }
228 #define CONFIG_SYS_NAND_ECCSIZE         512
229 #define CONFIG_SYS_NAND_ECCBYTES        3
230 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
231
232 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
233 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
234
235 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
236                                          CONFIG_SPL_TEXT_BASE)
237
238 /*
239  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
240  * older x-loader implementations. And move the BSS area so that it
241  * doesn't overlap with TEXT_BASE.
242  */
243 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
244 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
245
246 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
247 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
248
249 /* EEPROM */
250 #define CONFIG_ENV_EEPROM_IS_ON_I2C
251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
252 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
254 #define CONFIG_SYS_EEPROM_SIZE                  256
255
256 #endif /* __CONFIG_H */