Merge branch 'master' of git://git.denx.de/u-boot-x86
[platform/kernel/u-boot.git] / include / configs / cm_t335.h
1 /*
2  * Config file for Compulab CM-T335 board
3  *
4  * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
5  *
6  * Author: Ilya Ledvich <ilya@compulab.co.il>
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #ifndef __CONFIG_CM_T335_H
12 #define __CONFIG_CM_T335_H
13
14 #define CONFIG_CM_T335
15 #define CONFIG_NAND
16
17 #include <configs/ti_am335x_common.h>
18
19 #undef CONFIG_BOARD_LATE_INIT
20 #undef CONFIG_SPI
21 #undef CONFIG_OMAP3_SPI
22 #undef CONFIG_SPL_OS_BOOT
23 #undef CONFIG_BOOTCOUNT_LIMIT
24 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
25
26 #undef CONFIG_MAX_RAM_BANK_SIZE
27 #define CONFIG_MAX_RAM_BANK_SIZE        (512 << 20)     /* 512MB */
28
29 #define CONFIG_OMAP_COMMON
30
31 #define MACH_TYPE_CM_T335               4586    /* Until the next sync */
32 #define CONFIG_MACH_TYPE                MACH_TYPE_CM_T335
33
34 /* Clock Defines */
35 #define V_OSCK                          25000000  /* Clock output from T2 */
36 #define V_SCLK                          (V_OSCK)
37
38 #define CONFIG_ENV_SIZE                 (16 << 10)      /* 16 KiB */
39
40 #ifndef CONFIG_SPL_BUILD
41 #define MMCARGS \
42         "mmcdev=0\0" \
43         "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
44         "mmcrootfstype=ext4\0" \
45         "mmcargs=setenv bootargs console=${console} " \
46                 "root=${mmcroot} " \
47                 "rootfstype=${mmcrootfstype}\0" \
48         "mmcboot=echo Booting from mmc ...; " \
49                 "run mmcargs; " \
50                 "bootm ${loadaddr}\0"
51
52 #define NANDARGS \
53         "mtdids=" MTDIDS_DEFAULT "\0" \
54         "mtdparts=" MTDPARTS_DEFAULT "\0" \
55         "nandroot=ubi0:rootfs rw\0" \
56         "nandrootfstype=ubifs\0" \
57         "nandargs=setenv bootargs console=${console} " \
58                 "root=${nandroot} " \
59                 "rootfstype=${nandrootfstype} " \
60                 "ubi.mtd=${rootfs_name}\0" \
61         "nandboot=echo Booting from nand ...; " \
62                 "run nandargs; " \
63                 "nboot ${loadaddr} nand0 900000; " \
64                 "bootm ${loadaddr}\0"
65
66 #define CONFIG_EXTRA_ENV_SETTINGS \
67         "loadaddr=82000000\0" \
68         "console=ttyO0,115200n8\0" \
69         "rootfs_name=rootfs\0" \
70         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
71         "bootscript=echo Running bootscript from mmc ...; " \
72                 "source ${loadaddr}\0" \
73         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
74         MMCARGS \
75         NANDARGS
76
77 #define CONFIG_BOOTCOMMAND \
78         "mmc dev ${mmcdev}; if mmc rescan; then " \
79                 "if run loadbootscript; then " \
80                         "run bootscript; " \
81                 "else " \
82                         "if run loaduimage; then " \
83                                 "run mmcboot; " \
84                         "else run nandboot; " \
85                         "fi; " \
86                 "fi; " \
87         "else run nandboot; fi"
88 #endif /* CONFIG_SPL_BUILD */
89
90 #define CONFIG_TIMESTAMP
91 #define CONFIG_SYS_AUTOLOAD             "no"
92
93 /* Serial console configuration */
94 #define CONFIG_CONS_INDEX               1
95 #define CONFIG_SERIAL1                  1       /* UART0 */
96
97 /* NS16550 Configuration */
98 #define CONFIG_SYS_NS16550_COM1         0x44e09000      /* UART0 */
99 #define CONFIG_SYS_NS16550_COM2         0x48022000      /* UART1 */
100 #define CONFIG_BAUDRATE                 115200
101
102 /* I2C Configuration */
103 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* Main EEPROM */
104 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
105 #define CONFIG_SYS_I2C_EEPROM_BUS       0
106
107 /* SPL */
108 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/am33xx/u-boot-spl.lds"
109
110 /* Network. */
111 #define CONFIG_PHY_GIGE
112 #define CONFIG_PHYLIB
113 #define CONFIG_PHY_ATHEROS
114
115 /* NAND support */
116 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
117 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
118                                          CONFIG_SYS_NAND_PAGE_SIZE)
119 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
120 #define CONFIG_SYS_NAND_OOBSIZE         64
121 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
122 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
123 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
124                                          10, 11, 12, 13, 14, 15, 16, 17, \
125                                          18, 19, 20, 21, 22, 23, 24, 25, \
126                                          26, 27, 28, 29, 30, 31, 32, 33, \
127                                          34, 35, 36, 37, 38, 39, 40, 41, \
128                                          42, 43, 44, 45, 46, 47, 48, 49, \
129                                          50, 51, 52, 53, 54, 55, 56, 57, }
130
131 #define CONFIG_SYS_NAND_ECCSIZE         512
132 #define CONFIG_SYS_NAND_ECCBYTES        14
133
134 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
135
136 #undef CONFIG_SYS_NAND_U_BOOT_OFFS
137 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x200000
138
139 #define CONFIG_CMD_NAND
140 #define MTDIDS_DEFAULT                  "nand0=nand"
141 #define MTDPARTS_DEFAULT                "mtdparts=nand:2m(spl)," \
142                                         "1m(u-boot),1m(u-boot-env)," \
143                                         "1m(dtb),4m(splash)," \
144                                         "6m(kernel),-(rootfs)"
145 #define CONFIG_ENV_IS_IN_NAND
146 #define CONFIG_ENV_OFFSET               0x300000 /* environment starts here */
147 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB */
148 #define CONFIG_SYS_NAND_ONFI_DETECTION
149 #ifdef CONFIG_SPL_OS_BOOT
150 #define CONFIG_CMD_SPL_NAND_OFS         0x400000 /* un-assigned: (using dtb) */
151 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
152 #define CONFIG_CMD_SPL_WRITE_SIZE       0x2000
153 #endif
154
155 /* GPIO pin + bank to pin ID mapping */
156 #define GPIO_PIN(_bank, _pin)           ((_bank << 5) + _pin)
157
158 /* Status LED */
159 #define CONFIG_STATUS_LED
160 #define CONFIG_GPIO_LED
161 #define CONFIG_BOARD_SPECIFIC_LED
162 #define STATUS_LED_BIT                  GPIO_PIN(2, 0)
163 /* Status LED polarity is inversed, so init it in the "off" state */
164 #define STATUS_LED_STATE                STATUS_LED_OFF
165 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
166 #define STATUS_LED_BOOT                 0
167
168 /* EEPROM */
169 #define CONFIG_CMD_EEPROM
170 #define CONFIG_ENV_EEPROM_IS_ON_I2C
171 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
172 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
173 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
174 #define CONFIG_SYS_EEPROM_SIZE                  256
175
176 #define CONFIG_CMD_EEPROM_LAYOUT
177 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
178
179 #ifndef CONFIG_SPL_BUILD
180 /*
181  * Enable PCA9555 at I2C0-0x26.
182  * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
183  */
184 #define CONFIG_PCA953X
185 #define CONFIG_CMD_PCA953X
186 #define CONFIG_CMD_PCA953X_INFO
187 #define CONFIG_SYS_I2C_PCA953X_ADDR     0x26
188 #define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x26, 16} }
189 #endif /* CONFIG_SPL_BUILD */
190
191 #endif  /* __CONFIG_CM_T335_H */
192