2 * Config file for Compulab CM-T335 board
4 * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
6 * Author: Ilya Ledvich <ilya@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef __CONFIG_CM_T335_H
12 #define __CONFIG_CM_T335_H
14 #define CONFIG_CM_T335
17 #include <configs/ti_am335x_common.h>
20 #undef CONFIG_OMAP3_SPI
21 #undef CONFIG_BOOTCOUNT_LIMIT
22 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
24 #undef CONFIG_MAX_RAM_BANK_SIZE
25 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
27 #define MACH_TYPE_CM_T335 4586 /* Until the next sync */
28 #define CONFIG_MACH_TYPE MACH_TYPE_CM_T335
31 #define V_OSCK 25000000 /* Clock output from T2 */
32 #define V_SCLK (V_OSCK)
34 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
36 #ifndef CONFIG_SPL_BUILD
39 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
40 "mmcrootfstype=ext4\0" \
41 "mmcargs=setenv bootargs console=${console} " \
43 "rootfstype=${mmcrootfstype}\0" \
44 "mmcboot=echo Booting from mmc ...; " \
49 "mtdids=" MTDIDS_DEFAULT "\0" \
50 "mtdparts=" MTDPARTS_DEFAULT "\0" \
51 "nandroot=ubi0:rootfs rw\0" \
52 "nandrootfstype=ubifs\0" \
53 "nandargs=setenv bootargs console=${console} " \
55 "rootfstype=${nandrootfstype} " \
56 "ubi.mtd=${rootfs_name}\0" \
57 "nandboot=echo Booting from nand ...; " \
59 "nboot ${loadaddr} nand0 900000; " \
62 #define CONFIG_EXTRA_ENV_SETTINGS \
63 "loadaddr=82000000\0" \
64 "console=ttyO0,115200n8\0" \
65 "rootfs_name=rootfs\0" \
66 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
67 "bootscript=echo Running bootscript from mmc ...; " \
68 "source ${loadaddr}\0" \
69 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
73 #define CONFIG_BOOTCOMMAND \
74 "mmc dev ${mmcdev}; if mmc rescan; then " \
75 "if run loadbootscript; then " \
78 "if run loaduimage; then " \
80 "else run nandboot; " \
83 "else run nandboot; fi"
84 #endif /* CONFIG_SPL_BUILD */
86 #define CONFIG_TIMESTAMP
87 #define CONFIG_SYS_AUTOLOAD "no"
89 /* Serial console configuration */
90 #define CONFIG_CONS_INDEX 1
91 #define CONFIG_SERIAL1 1 /* UART0 */
93 /* NS16550 Configuration */
94 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
95 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
96 #define CONFIG_BAUDRATE 115200
98 /* I2C Configuration */
99 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
100 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
101 #define CONFIG_SYS_I2C_EEPROM_BUS 0
104 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
107 #define CONFIG_PHY_GIGE
108 #define CONFIG_PHYLIB
109 #define CONFIG_PHY_ATHEROS
112 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
113 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
114 CONFIG_SYS_NAND_PAGE_SIZE)
115 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
116 #define CONFIG_SYS_NAND_OOBSIZE 64
117 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
118 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
119 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
120 10, 11, 12, 13, 14, 15, 16, 17, \
121 18, 19, 20, 21, 22, 23, 24, 25, \
122 26, 27, 28, 29, 30, 31, 32, 33, \
123 34, 35, 36, 37, 38, 39, 40, 41, \
124 42, 43, 44, 45, 46, 47, 48, 49, \
125 50, 51, 52, 53, 54, 55, 56, 57, }
127 #define CONFIG_SYS_NAND_ECCSIZE 512
128 #define CONFIG_SYS_NAND_ECCBYTES 14
130 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
132 #undef CONFIG_SYS_NAND_U_BOOT_OFFS
133 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
135 #define CONFIG_CMD_NAND
136 #define MTDIDS_DEFAULT "nand0=nand"
137 #define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \
138 "1m(u-boot),1m(u-boot-env)," \
139 "1m(dtb),4m(splash)," \
140 "6m(kernel),-(rootfs)"
141 #define CONFIG_ENV_IS_IN_NAND
142 #define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */
143 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
144 #define CONFIG_SYS_NAND_ONFI_DETECTION
145 #ifdef CONFIG_SPL_OS_BOOT
146 #define CONFIG_CMD_SPL_NAND_OFS 0x400000 /* un-assigned: (using dtb) */
147 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
148 #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
151 /* GPIO pin + bank to pin ID mapping */
152 #define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin)
155 /* Status LED polarity is inversed, so init it in the "off" state */
158 #define CONFIG_CMD_EEPROM
159 #define CONFIG_ENV_EEPROM_IS_ON_I2C
160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
161 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
162 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
163 #define CONFIG_SYS_EEPROM_SIZE 256
165 #define CONFIG_CMD_EEPROM_LAYOUT
166 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
168 #ifndef CONFIG_SPL_BUILD
170 * Enable PCA9555 at I2C0-0x26.
171 * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
173 #define CONFIG_PCA953X
174 #define CONFIG_CMD_PCA953X
175 #define CONFIG_CMD_PCA953X_INFO
176 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x26
177 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} }
178 #endif /* CONFIG_SPL_BUILD */
180 #endif /* __CONFIG_CM_T335_H */