include/configs/cm_t335.h

   1 /*
   2  * Config file for Compulab CM-T335 board
   3  *
   4  * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Ilya Ledvich <ilya@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_CM_T335_H
  12 #define __CONFIG_CM_T335_H
  13
  14 #define CONFIG_CM_T335
  15 #define CONFIG_NAND
  16
  17 #include <configs/ti_am335x_common.h>
  18
  19 #undef CONFIG_BOARD_LATE_INIT
  20 #undef CONFIG_SPI
  21 #undef CONFIG_OMAP3_SPI
  22 #undef CONFIG_BOOTCOUNT_LIMIT
  23 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
  24
  25 #undef CONFIG_MAX_RAM_BANK_SIZE
  26 #define CONFIG_MAX_RAM_BANK_SIZE        (512 << 20)     /* 512MB */
  27
  28 #define CONFIG_OMAP_COMMON
  29
  30 #define MACH_TYPE_CM_T335               4586    /* Until the next sync */
  31 #define CONFIG_MACH_TYPE                MACH_TYPE_CM_T335
  32
  33 /* Clock Defines */
  34 #define V_OSCK                          25000000  /* Clock output from T2 */
  35 #define V_SCLK                          (V_OSCK)
  36
  37 #define CONFIG_ENV_SIZE                 (16 << 10)      /* 16 KiB */
  38
  39 #ifndef CONFIG_SPL_BUILD
  40 #define MMCARGS \
  41         "mmcdev=0\0" \
  42         "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
  43         "mmcrootfstype=ext4\0" \
  44         "mmcargs=setenv bootargs console=${console} " \
  45                 "root=${mmcroot} " \
  46                 "rootfstype=${mmcrootfstype}\0" \
  47         "mmcboot=echo Booting from mmc ...; " \
  48                 "run mmcargs; " \
  49                 "bootm ${loadaddr}\0"
  50
  51 #define NANDARGS \
  52         "mtdids=" MTDIDS_DEFAULT "\0" \
  53         "mtdparts=" MTDPARTS_DEFAULT "\0" \
  54         "nandroot=ubi0:rootfs rw\0" \
  55         "nandrootfstype=ubifs\0" \
  56         "nandargs=setenv bootargs console=${console} " \
  57                 "root=${nandroot} " \
  58                 "rootfstype=${nandrootfstype} " \
  59                 "ubi.mtd=${rootfs_name}\0" \
  60         "nandboot=echo Booting from nand ...; " \
  61                 "run nandargs; " \
  62                 "nboot ${loadaddr} nand0 900000; " \
  63                 "bootm ${loadaddr}\0"
  64
  65 #define CONFIG_EXTRA_ENV_SETTINGS \
  66         "loadaddr=82000000\0" \
  67         "console=ttyO0,115200n8\0" \
  68         "rootfs_name=rootfs\0" \
  69         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  70         "bootscript=echo Running bootscript from mmc ...; " \
  71                 "source ${loadaddr}\0" \
  72         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  73         MMCARGS \
  74         NANDARGS
  75
  76 #define CONFIG_BOOTCOMMAND \
  77         "mmc dev ${mmcdev}; if mmc rescan; then " \
  78                 "if run loadbootscript; then " \
  79                         "run bootscript; " \
  80                 "else " \
  81                         "if run loaduimage; then " \
  82                                 "run mmcboot; " \
  83                         "else run nandboot; " \
  84                         "fi; " \
  85                 "fi; " \
  86         "else run nandboot; fi"
  87 #endif /* CONFIG_SPL_BUILD */
  88
  89 #define CONFIG_TIMESTAMP
  90 #define CONFIG_SYS_AUTOLOAD             "no"
  91
  92 /* Serial console configuration */
  93 #define CONFIG_CONS_INDEX               1
  94 #define CONFIG_SERIAL1                  1       /* UART0 */
  95
  96 /* NS16550 Configuration */
  97 #define CONFIG_SYS_NS16550_COM1         0x44e09000      /* UART0 */
  98 #define CONFIG_SYS_NS16550_COM2         0x48022000      /* UART1 */
  99 #define CONFIG_BAUDRATE                 115200
 100
 101 /* I2C Configuration */
 102 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* Main EEPROM */
 103 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 104 #define CONFIG_SYS_I2C_EEPROM_BUS       0
 105
 106 /* SPL */
 107 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/am33xx/u-boot-spl.lds"
 108
 109 /* Network. */
 110 #define CONFIG_PHY_GIGE
 111 #define CONFIG_PHYLIB
 112 #define CONFIG_PHY_ATHEROS
 113
 114 /* NAND support */
 115 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 116 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
 117                                          CONFIG_SYS_NAND_PAGE_SIZE)
 118 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 119 #define CONFIG_SYS_NAND_OOBSIZE         64
 120 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 121 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 122 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
 123                                          10, 11, 12, 13, 14, 15, 16, 17, \
 124                                          18, 19, 20, 21, 22, 23, 24, 25, \
 125                                          26, 27, 28, 29, 30, 31, 32, 33, \
 126                                          34, 35, 36, 37, 38, 39, 40, 41, \
 127                                          42, 43, 44, 45, 46, 47, 48, 49, \
 128                                          50, 51, 52, 53, 54, 55, 56, 57, }
 129
 130 #define CONFIG_SYS_NAND_ECCSIZE         512
 131 #define CONFIG_SYS_NAND_ECCBYTES        14
 132
 133 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 134
 135 #undef CONFIG_SYS_NAND_U_BOOT_OFFS
 136 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x200000
 137
 138 #define CONFIG_CMD_NAND
 139 #define MTDIDS_DEFAULT                  "nand0=nand"
 140 #define MTDPARTS_DEFAULT                "mtdparts=nand:2m(spl)," \
 141                                         "1m(u-boot),1m(u-boot-env)," \
 142                                         "1m(dtb),4m(splash)," \
 143                                         "6m(kernel),-(rootfs)"
 144 #define CONFIG_ENV_IS_IN_NAND
 145 #define CONFIG_ENV_OFFSET               0x300000 /* environment starts here */
 146 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB */
 147 #define CONFIG_SYS_NAND_ONFI_DETECTION
 148 #ifdef CONFIG_SPL_OS_BOOT
 149 #define CONFIG_CMD_SPL_NAND_OFS         0x400000 /* un-assigned: (using dtb) */
 150 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
 151 #define CONFIG_CMD_SPL_WRITE_SIZE       0x2000
 152 #endif
 153
 154 /* GPIO pin + bank to pin ID mapping */
 155 #define GPIO_PIN(_bank, _pin)           ((_bank << 5) + _pin)
 156
 157 /* Status LED */
 158 #define CONFIG_STATUS_LED
 159 #define CONFIG_GPIO_LED
 160 #define CONFIG_BOARD_SPECIFIC_LED
 161 #define STATUS_LED_BIT                  GPIO_PIN(2, 0)
 162 /* Status LED polarity is inversed, so init it in the "off" state */
 163 #define STATUS_LED_STATE                STATUS_LED_OFF
 164 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 165 #define STATUS_LED_BOOT                 0
 166
 167 /* EEPROM */
 168 #define CONFIG_CMD_EEPROM
 169 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 170 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 171 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 172 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 173 #define CONFIG_SYS_EEPROM_SIZE                  256
 174
 175 #define CONFIG_CMD_EEPROM_LAYOUT
 176 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
 177
 178 #ifndef CONFIG_SPL_BUILD
 179 /*
 180  * Enable PCA9555 at I2C0-0x26.
 181  * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
 182  */
 183 #define CONFIG_PCA953X
 184 #define CONFIG_CMD_PCA953X
 185 #define CONFIG_CMD_PCA953X_INFO
 186 #define CONFIG_SYS_I2C_PCA953X_ADDR     0x26
 187 #define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x26, 16} }
 188 #endif /* CONFIG_SPL_BUILD */
 189
 190 #endif  /* __CONFIG_CM_T335_H */
 191