2 * Config file for Compulab CM-FX6 board
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef __CONFIG_CM_FX6_H
12 #define __CONFIG_CM_FX6_H
14 #include <asm/arch/imx-regs.h>
15 #include <config_distro_defaults.h>
16 #include "mx6_common.h"
20 #define CONFIG_SYS_LITTLE_ENDIAN
21 #define CONFIG_MACH_TYPE 4273
23 #ifndef CONFIG_SPL_BUILD
27 #define CONFIG_DM_GPIO
28 #define CONFIG_CMD_GPIO
30 #define CONFIG_DM_SERIAL
31 #define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
34 /* Display information on boot */
35 #define CONFIG_DISPLAY_CPUINFO
36 #define CONFIG_DISPLAY_BOARDINFO
37 #define CONFIG_TIMESTAMP
40 #include <config_cmd_default.h>
41 #define CONFIG_CMD_GREPENV
42 #undef CONFIG_CMD_FLASH
43 #undef CONFIG_CMD_LOADB
44 #undef CONFIG_CMD_LOADS
45 #undef CONFIG_CMD_XIMG
46 #undef CONFIG_CMD_FPGA
47 #undef CONFIG_CMD_IMLS
51 #define CONFIG_CMD_MMC
52 #define CONFIG_GENERIC_MMC
53 #define CONFIG_FSL_ESDHC
54 #define CONFIG_FSL_USDHC
55 #define CONFIG_SYS_FSL_USDHC_NUM 3
56 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
59 #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
60 #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
61 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
62 #define CONFIG_NR_DRAM_BANKS 2
63 #define CONFIG_SYS_MEMTEST_START 0x10000000
64 #define CONFIG_SYS_MEMTEST_END 0x10010000
65 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
66 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
67 #define CONFIG_SYS_INIT_SP_OFFSET \
68 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
69 #define CONFIG_SYS_INIT_SP_ADDR \
70 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
73 #define CONFIG_MXC_UART
74 #define CONFIG_MXC_UART_BASE UART4_BASE
75 #define CONFIG_BAUDRATE 115200
76 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
79 #define CONFIG_SYS_PROMPT "CM-FX6 # "
80 #define CONFIG_SYS_CBSIZE 1024
81 #define CONFIG_SYS_MAXARGS 16
82 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
83 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
84 sizeof(CONFIG_SYS_PROMPT) + 16)
87 #define CONFIG_SYS_NO_FLASH
89 #define CONFIG_SF_DEFAULT_BUS 0
90 #define CONFIG_SF_DEFAULT_CS 0
91 #define CONFIG_SF_DEFAULT_SPEED 25000000
92 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
95 #define CONFIG_ENV_OVERWRITE
96 #define CONFIG_ENV_IS_IN_SPI_FLASH
97 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
98 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
99 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
100 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
101 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
102 #define CONFIG_ENV_SIZE (8 * 1024)
103 #define CONFIG_ENV_OFFSET (768 * 1024)
105 #define CONFIG_EXTRA_ENV_SETTINGS \
106 "kernel=uImage-cm-fx6\0" \
108 "loadaddr=0x10800000\0" \
109 "fdtaddr=0x11000000\0" \
110 "console=ttymxc3,115200\0" \
112 "bootscr=boot.scr\0" \
113 "bootm_low=18000000\0" \
114 "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
115 "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
116 "fdtfile=cm-fx6.dtb\0" \
117 "doboot=bootm ${loadaddr}\0" \
119 "setboottypez=setenv kernel zImage-cm-fx6;" \
120 "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
121 "setenv loadfdt true;\0" \
122 "setboottypem=setenv kernel uImage-cm-fx6;" \
123 "setenv doboot bootm ${loadaddr};" \
124 "setenv loadfdt false;\0"\
125 "run_eboot=echo Starting EBOOT ...; "\
126 "mmc dev ${mmcdev} && " \
127 "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
129 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
130 "loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \
131 "mmcbootscript=echo Running bootscript from mmc ...; "\
132 "source ${loadaddr}\0" \
133 "mmcargs=setenv bootargs console=${console} " \
136 "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
137 "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
138 "mmcboot=echo Booting from mmc ...; " \
142 "sataroot=/dev/sda2 rw rootwait\0" \
143 "sataargs=setenv bootargs console=${console} " \
144 "root=${sataroot} " \
146 "loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \
147 "satabootscript=echo Running bootscript from sata ...; " \
148 "source ${loadaddr}\0" \
149 "sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \
150 "sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \
151 "sataboot=echo Booting from sata ...; "\
154 "nandroot=/dev/mtdblock4 rw\0" \
155 "nandrootfstype=ubifs\0" \
156 "nandargs=setenv bootargs console=${console} " \
157 "root=${nandroot} " \
158 "rootfstype=${nandrootfstype} " \
160 "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
161 "nandboot=echo Booting from nand ...; " \
163 "nand read ${loadaddr} 0 780000; " \
164 "if ${loadfdt}; then " \
168 "boot=mmc dev ${mmcdev}; " \
169 "if mmc rescan; then " \
170 "if run loadmmcbootscript; then " \
171 "run mmcbootscript;" \
173 "if run mmcloadkernel; then " \
174 "if ${loadfdt}; then " \
181 "if sata init; then " \
182 "if run loadsatabootscript; then " \
183 "run satabootscript;" \
185 "if run sataloadkernel; then " \
186 "if ${loadfdt}; then " \
187 "run sataloadfdt; " \
195 #define CONFIG_BOOTCOMMAND \
196 "run setboottypem; run boot"
200 #define CONFIG_MXC_SPI
201 #define CONFIG_SPI_FLASH
202 #define CONFIG_SPI_FLASH_ATMEL
203 #define CONFIG_SPI_FLASH_EON
204 #define CONFIG_SPI_FLASH_GIGADEVICE
205 #define CONFIG_SPI_FLASH_MACRONIX
206 #define CONFIG_SPI_FLASH_SPANSION
207 #define CONFIG_SPI_FLASH_STMICRO
208 #define CONFIG_SPI_FLASH_SST
209 #define CONFIG_SPI_FLASH_WINBOND
212 #ifndef CONFIG_SPL_BUILD
213 #define CONFIG_CMD_NAND
214 #define CONFIG_SYS_NAND_BASE 0x40000000
215 #define CONFIG_SYS_NAND_MAX_CHIPS 1
216 #define CONFIG_SYS_MAX_NAND_DEVICE 1
217 #define CONFIG_NAND_MXS
218 #define CONFIG_SYS_NAND_ONFI_DETECTION
219 /* APBH DMA is required for NAND support */
220 #define CONFIG_APBH_DMA
221 #define CONFIG_APBH_DMA_BURST
222 #define CONFIG_APBH_DMA_BURST8
226 #define CONFIG_FEC_MXC
227 #define CONFIG_FEC_MXC_PHYADDR 0
228 #define CONFIG_FEC_XCV_TYPE RGMII
229 #define IMX_FEC_BASE ENET_BASE_ADDR
230 #define CONFIG_PHYLIB
231 #define CONFIG_PHY_ATHEROS
233 #define CONFIG_ETHPRIME "FEC0"
234 #define CONFIG_ARP_TIMEOUT 200UL
235 #define CONFIG_NET_RETRY_COUNT 5
238 #define CONFIG_CMD_USB
239 #define CONFIG_USB_EHCI
240 #define CONFIG_USB_EHCI_MX6
241 #define CONFIG_USB_STORAGE
242 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
243 #define CONFIG_MXC_USB_FLAGS 0
244 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
245 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
248 #define CONFIG_CMD_I2C
249 #define CONFIG_SYS_I2C
250 #define CONFIG_SYS_I2C_MXC
251 #define CONFIG_SYS_I2C_SPEED 100000
252 #define CONFIG_SYS_MXC_I2C3_SPEED 400000
254 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
255 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
256 #define CONFIG_SYS_I2C_EEPROM_BUS 2
259 #define CONFIG_CMD_SATA
260 #define CONFIG_SYS_SATA_MAX_DEVICE 1
261 #define CONFIG_LIBATA
263 #define CONFIG_DWC_AHSATA
264 #define CONFIG_DWC_AHSATA_PORT_ID 0
265 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
268 #define CONFIG_MXC_GPIO
271 #define CONFIG_ZERO_BOOTDELAY_CHECK
272 #define CONFIG_LOADADDR 0x10800000
273 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
274 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
275 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
276 #define CONFIG_SETUP_MEMORY_TAGS
277 #define CONFIG_INITRD_TAG
278 #define CONFIG_REVISION_TAG
279 #define CONFIG_SERIAL_TAG
282 #define CONFIG_SYS_GENERIC_BOARD
283 #define CONFIG_STACKSIZE (128 * 1024)
284 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
285 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
286 #define CONFIG_OF_BOARD_SETUP
289 #include "imx6_spl.h"
290 #define CONFIG_SPL_BOARD_INIT
291 #define CONFIG_SPL_MMC_SUPPORT
292 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */
293 #define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
294 #define CONFIG_SPL_SPI_SUPPORT
295 #define CONFIG_SPL_SPI_FLASH_SUPPORT
296 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
297 #define CONFIG_SPL_SPI_LOAD
299 #endif /* __CONFIG_CM_FX6_H */