2 * (C) Copyright 2003-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_DISPLAY_BOARDINFO
14 * High Level Configuration Options
16 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
17 #define CONFIG_CM5200 1 /* ... on CM5200 platform */
19 #define CONFIG_SYS_TEXT_BASE 0xfc000000
21 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
26 #define CONFIG_CMD_BSP
27 #define CONFIG_CMD_DATE
28 #define CONFIG_CMD_DIAG
29 #define CONFIG_CMD_JFFS2
30 #define CONFIG_CMD_REGINFO
33 * Serial console configuration
35 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
36 #define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */
37 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
38 #define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */
41 * Ethernet configuration
43 #define CONFIG_MPC5xxx_FEC 1
44 #define CONFIG_MPC5xxx_FEC_MII100
45 #define CONFIG_PHY_ADDR 0x00
46 #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
47 /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
48 #define CONFIG_MISC_INIT_R 1
49 #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
54 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
55 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
56 /* List of I2C addresses to be verified by POST */
57 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
59 CONFIG_SYS_I2C_EEPROM}
61 /* display image timestamps */
62 #define CONFIG_TIMESTAMP 1
67 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
68 #define CONFIG_PREBOOT "echo;" \
69 "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
71 #undef CONFIG_BOOTARGS
74 * Default environment settings
76 #define CONFIG_EXTRA_ENV_SETTINGS \
78 "netmask=255.255.0.0\0" \
79 "ipaddr=192.168.160.33\0" \
80 "serverip=192.168.1.1\0" \
81 "gatewayip=192.168.1.1\0" \
83 "u-boot_addr=100000\0" \
84 "kernel_addr=200000\0" \
85 "kernel_addr_flash=fc0c0000\0" \
87 "fdt_addr_flash=fc0a0000\0" \
88 "ramdisk_addr=500000\0" \
89 "rootpath=/opt/eldk-4.1/ppc_6xx\0" \
90 "u-boot=/tftpboot/cm5200/u-boot.bin\0" \
91 "bootfile_fdt=/tftpboot/cm5200/uImage\0" \
92 "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
93 "load=tftp ${u-boot_addr} ${u-boot}\0" \
94 "update=prot off fc000000 +${filesize}; " \
95 "era fc000000 +${filesize}; " \
96 "cp.b ${u-boot_addr} fc000000 ${filesize}; " \
97 "prot on fc000000 +${filesize}\0" \
98 "nfsargs=setenv bootargs root=/dev/nfs rw " \
99 "nfsroot=${serverip}:${rootpath}\0" \
100 "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
101 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
102 "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \
103 "addcons=setenv bootargs ${bootargs} " \
104 "console=${console},${baudrate}\0" \
105 "addip=setenv bootargs ${bootargs} " \
106 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
107 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
108 "flash_flash=run flashargs addinit addip addcons;" \
109 "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \
110 "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \
111 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \
112 "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \
114 #define CONFIG_BOOTCOMMAND "run flash_flash"
117 * Low level configuration
121 * Clock configuration
123 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
124 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
129 #define CONFIG_SYS_MBAR 0xF0000000
130 #define CONFIG_SYS_SDRAM_BASE 0x00000000
131 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
133 #define CONFIG_SYS_LOWBOOT 1
135 /* Use ON-Chip SRAM until RAM will be available */
136 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
138 /* preserve space for the post_word at end of on-chip SRAM */
139 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
141 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
144 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
145 #define CONFIG_BOARD_TYPES 1 /* we use board_type */
147 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
150 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
151 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
152 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
155 * Flash configuration
157 #define CONFIG_SYS_FLASH_CFI 1
158 #define CONFIG_FLASH_CFI_DRIVER 1
159 #define CONFIG_SYS_FLASH_BASE 0xfc000000
160 /* we need these despite using CFI */
161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
162 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
163 #define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
165 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
166 #define CONFIG_SYS_RAMBOOT 1
167 #undef CONFIG_SYS_LOWBOOT
171 * Chip selects configuration
173 /* Boot Chipselect */
174 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
175 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
176 #define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */
177 /* use board_early_init_r to enable flash write in CS_BOOT */
178 #define CONFIG_BOARD_EARLY_INIT_R
180 /* Flash memory addressing */
181 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
182 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
184 /* No burst, dead cycle = 1 for CS0 (Flash) */
185 #define CONFIG_SYS_CS_BURST 0x00000000
186 #define CONFIG_SYS_CS_DEADCYCLE 0x00000001
189 * SDRAM configuration
190 * settings for k4s561632E-xx75, assuming XLB = 132 MHz
192 #define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */
193 #define SDRAM_CONTROL 0x514F0000
194 #define SDRAM_CONFIG1 0xE2333900
195 #define SDRAM_CONFIG2 0x8EE70000
200 #define CONFIG_CMD_MTDPARTS 1
201 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
202 #define CONFIG_FLASH_CFI_MTD
203 #define MTDIDS_DEFAULT "nor0=cm5200-0"
204 #define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
205 "384k(uboot),128k(env)," \
206 "128k(redund_env),128k(dtb)," \
207 "2m(kernel),27904k(rootfs)," \
213 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
214 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
215 #define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */
216 #define CONFIG_SYS_I2C_SLAVE 0x0
217 #define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
218 #define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */
223 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
228 #define CONFIG_USB_OHCI 1
229 #define CONFIG_USB_STORAGE 1
230 #define CONFIG_USB_CLOCK 0x0001BBBB
231 #define CONFIG_USB_CONFIG 0x00001000
232 /* Partitions (for USB) */
233 #define CONFIG_MAC_PARTITION 1
234 #define CONFIG_DOS_PARTITION 1
235 #define CONFIG_ISO_PARTITION 1
238 * Invoke our last_stage_init function - needed by fwupdate
240 #define CONFIG_LAST_STAGE_INIT 1
243 * Environment settings
245 #define CONFIG_ENV_IS_IN_FLASH 1
246 #define CONFIG_ENV_SIZE 0x10000
247 #define CONFIG_ENV_SECT_SIZE 0x20000
248 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
249 /* Configuration of redundant environment */
250 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
251 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
254 * Pin multiplexing configuration
258 * CS1/GPIO_WKUP_6: GPIO (default)
259 * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
261 * Ether: Ethernet 100Mbit with MD
262 * PCI_DIS: PCI controller disabled
264 * PSC3: SPI with UART3
268 #define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44
271 * Miscellaneous configurable options
273 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
274 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
275 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
276 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
277 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
279 #define CONFIG_SYS_ALT_MEMTEST 1
280 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
281 #define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */
283 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
286 * Various low-level settings
288 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
289 #define CONFIG_SYS_HID0_FINAL HID0_ICE
291 #define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */
294 * Cache Configuration
296 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
297 #ifdef CONFIG_CMD_KGDB
298 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
302 * Flat Device Tree support
304 #define OF_CPU "PowerPC,5200@0"
305 #define OF_SOC "soc5200@f0000000"
306 #define OF_TBCLK (bd->bi_busfreq / 4)
307 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
309 #endif /* __CONFIG_H */