2 * (C) Copyright 2003-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
30 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
31 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
32 #define CONFIG_CM5200 1 /* ... on CM5200 platform */
38 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
56 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
57 #include <cmd_confdefs.h>
61 * Serial console configuration
63 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
64 #define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */
65 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
66 #define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */
70 * Ethernet configuration
72 #define CONFIG_MPC5xxx_FEC 1
73 #define CONFIG_PHY_ADDR 0x00
74 #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
75 /* use misc_init_r() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */
76 #define CONFIG_MISC_INIT_R 1
77 #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
83 #define CONFIG_POST (CFG_POST_MEMORY | CFG_POST_CPU | CFG_POST_I2C)
84 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
85 /* List of I2C addresses to be verified by POST */
86 #define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM }
89 /* display image timestamps */
90 #define CONFIG_TIMESTAMP 1
96 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
97 #define CONFIG_PREBOOT "echo;" \
98 "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
100 #undef CONFIG_BOOTARGS
103 * Default environment settings
105 #define CONFIG_EXTRA_ENV_SETTINGS \
107 "netmask=255.255.0.0\0" \
108 "ipaddr=192.168.160.33\0" \
109 "serverip=192.168.1.1\0" \
110 "gatewayip=192.168.1.1\0" \
111 "console=ttyPSC0\0" \
112 "u-boot_addr=100000\0" \
113 "kernel_addr=200000\0" \
114 "kernel_addr_flash=fc0c0000\0" \
115 "fdt_addr=400000\0" \
116 "fdt_addr_flash=fc0a0000\0" \
117 "ramdisk_addr=500000\0" \
118 "rootpath=/opt/eldk-4.1/ppc_6xx\0" \
119 "u-boot=/tftpboot/cm5200/u-boot.bin\0" \
120 "bootfile_fdt=/tftpboot/cm5200/uImage\0" \
121 "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
122 "load=tftp ${u-boot_addr} ${u-boot}\0" \
123 "update=prot off fc000000 +${filesize}; " \
124 "era fc000000 +${filesize}; " \
125 "cp.b ${u-boot_addr} fc000000 ${filesize}; " \
126 "prot on fc000000 +${filesize}\0" \
127 "nfsargs=setenv bootargs root=/dev/nfs rw " \
128 "nfsroot=${serverip}:${rootpath}\0" \
129 "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
130 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
131 "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \
132 "addcons=setenv bootargs ${bootargs} " \
133 "console=${console},${baudrate}\0" \
134 "addip=setenv bootargs ${bootargs} " \
135 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
136 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
137 "flash_flash=run flashargs addinit addip addcons;" \
138 "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \
139 "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \
140 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \
141 "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \
143 #define CONFIG_BOOTCOMMAND "run flash_flash"
147 * Low level configuration
152 * Clock configuration
154 #define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
155 #define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
161 #define CFG_MBAR 0xF0000000
162 #define CFG_SDRAM_BASE 0x00000000
163 #define CFG_DEFAULT_MBAR 0x80000000
165 #define CFG_LOWBOOT 1
167 /* Use ON-Chip SRAM until RAM will be available */
168 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
170 /* preserve space for the post_word at end of on-chip SRAM */
171 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
173 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
176 #define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */
177 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
178 #define CONFIG_BOARD_TYPES 1 /* we use board_type */
180 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
182 #define CFG_MONITOR_BASE TEXT_BASE
183 #define CFG_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
184 #define CFG_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
185 #define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
188 * Flash configuration
190 #define CFG_FLASH_CFI 1
191 #define CFG_FLASH_CFI_DRIVER 1
192 #define CFG_FLASH_BASE 0xfc000000
193 /* we need these despite using CFI */
194 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
195 #define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
196 #define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */
199 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
200 #define CFG_RAMBOOT 1
206 * Chip selects configuration
208 /* Boot Chipselect */
209 #define CFG_BOOTCS_START CFG_FLASH_BASE
210 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
211 #define CFG_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */
212 /* use board_early_init_r to enable flash write in CS_BOOT */
213 #define CONFIG_BOARD_EARLY_INIT_R
215 /* Flash memory addressing */
216 #define CFG_CS0_START CFG_FLASH_BASE
217 #define CFG_CS0_SIZE CFG_FLASH_SIZE
219 /* No burst, dead cycle = 1 for CS0 (Flash) */
220 #define CFG_CS_BURST 0x00000000
221 #define CFG_CS_DEADCYCLE 0x00000001
225 * SDRAM configuration
226 * settings for k4s561632E-xx75, assuming XLB = 132 MHz
228 #define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */
229 #define SDRAM_CONTROL 0x514F0000
230 #define SDRAM_CONFIG1 0xE2333900
231 #define SDRAM_CONFIG2 0x8EE70000
238 #define CONFIG_JFFS2_CMDLINE 1
239 #define MTDIDS_DEFAULT "nor0=cm5200-0"
240 #define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
241 "384k(uboot),128k(env)," \
242 "128k(redund_env),128k(dtb)," \
243 "2m(kernel),27904k(rootfs)," \
250 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
251 #define CFG_I2C_MODULE 2 /* Select I2C module #2 */
252 #define CFG_I2C_SPEED 40000 /* 40 kHz */
253 #define CFG_I2C_SLAVE 0x0
254 #define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
255 #define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */
261 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
267 #define CONFIG_USB_OHCI 1
268 #define CONFIG_USB_STORAGE 1
269 #define CONFIG_USB_CLOCK 0x0001BBBB
270 #define CONFIG_USB_CONFIG 0x00001000
271 /* Partitions (for USB) */
272 #define CONFIG_MAC_PARTITION 1
273 #define CONFIG_DOS_PARTITION 1
274 #define CONFIG_ISO_PARTITION 1
277 * Invoke our last_stage_init function - needed by fwupdate
279 #define CONFIG_LAST_STAGE_INIT 1
282 * Environment settings
284 #define CFG_ENV_IS_IN_FLASH 1
285 #define CFG_ENV_SIZE 0x10000
286 #define CFG_ENV_SECT_SIZE 0x20000
287 #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
288 /* Configuration of redundant environment */
289 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
290 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
294 * Pin multiplexing configuration
298 * CS1/GPIO_WKUP_6: GPIO (default)
299 * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
301 * Ether: Ethernet 100Mbit with MD
302 * PCI_DIS: PCI controller disabled
304 * PSC3: SPI with UART3
308 #define CFG_GPS_PORT_CONFIG 0x10559C44
312 * Miscellaneous configurable options
314 #define CFG_LONGHELP 1 /* undef to save memory */
315 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
316 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
317 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
318 #define CFG_MAXARGS 16 /* max number of command args */
319 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
321 #define CFG_ALT_MEMTEST 1
322 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
323 #define CFG_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */
325 #define CONFIG_LOOPW 1
327 #define CFG_LOAD_ADDR 0x100000 /* default load address */
328 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
332 * Various low-level settings
334 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
335 #define CFG_HID0_FINAL HID0_ICE
337 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
338 #define BOOTFLAG_WARM 0x02 /* Software reboot */
340 #define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */
344 * Cache Configuration
346 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
347 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
348 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
353 * Flat Device Tree support
355 #define CONFIG_OF_LIBFDT 1
356 #define CONFIG_OF_BOARD_SETUP 1
357 #define OF_CPU "PowerPC,5200@0"
358 #define OF_SOC "soc5200@f0000000"
359 #define OF_TBCLK (bd->bi_busfreq / 4)
360 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
362 #endif /* __CONFIG_H */