1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015 CompuLab, Ltd.
5 * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module.
8 #ifndef __CL_SOM_IMX7_CONFIG_H
9 #define __CL_SOM_IMX7_CONFIG_H
11 #include "mx7_common.h"
13 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
15 /* Size of malloc() pool */
16 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
18 #define CONFIG_BOARD_LATE_INIT
21 #define CONFIG_FEC_MXC
22 #define CONFIG_FEC_XCV_TYPE RGMII
23 #define CONFIG_ETHPRIME "FEC"
24 #define CONFIG_FEC_MXC_PHYADDR 0
27 #define CONFIG_PHY_ATHEROS
29 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR
33 #define CONFIG_POWER_I2C
34 #define CONFIG_POWER_PFUZE3000
35 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
38 #define CONFIG_SYS_I2C
39 #define CONFIG_SYS_I2C_MXC
40 #define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */
41 #define CONFIG_SYS_I2C_SPEED 100000
42 #define SYS_I2C_BUS_SOM 0
44 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
45 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
46 #define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM
48 #define CONFIG_PCA953X
49 #define CONFIG_CMD_PCA953X
50 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
51 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
53 #undef CONFIG_SYS_AUTOLOAD
54 #undef CONFIG_EXTRA_ENV_SETTINGS
55 #undef CONFIG_BOOTCOMMAND
57 #define CONFIG_SYS_AUTOLOAD "no"
59 #define CONFIG_EXTRA_ENV_SETTINGS \
62 "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \
63 "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \
64 "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\0" \
65 "bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\0" \
66 "storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\0" \
69 "fdt_high=0xffffffff\0" \
70 "initrd_high=0xffffffff\0" \
71 "fdtfile=imx7d-sbc-imx7.dtb\0" \
72 "fdtaddr=0x83000000\0" \
73 "mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \
74 "usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \
75 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
76 "usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \
77 "doboot=bootz ${loadaddr} - ${fdtaddr}\0" \
78 "mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \
79 "mmcargs=setenv bootargs console=${console},${baudrate} " \
80 "root=/dev/mmcblk${mmcblk}p2 rootwait rw\0" \
82 "if run mmc_config; then " \
83 "setenv storagetype mmc;" \
84 "setenv storagedev ${mmcdev}:${mmcpart};" \
85 "if run loadscript; then " \
90 "if run mmc_config; then " \
91 "setenv storagetype mmc;" \
92 "setenv storagedev ${mmcdev}:${mmcpart};" \
93 "if run loadkernel; then " \
94 "if run loadfdt; then " \
95 "run storagebootcmd;" \
99 "sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; " \
100 "run mmcbootscript\0" \
101 "usbbootscript=setenv usbdev ${usbdev_def}; " \
102 "setenv storagetype usb;" \
103 "setenv storagedev ${usbdev}:${usbpart};" \
104 "if run loadscript; then " \
107 "sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\0" \
108 "emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \
109 "emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \
111 #define CONFIG_BOOTCOMMAND \
112 "echo SD boot attempt ...; run sdbootscript; run sdboot; " \
113 "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \
114 "echo USB boot attempt ...; run usbbootscript; "
116 #define CONFIG_SYS_MEMTEST_START 0x80000000
117 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
119 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
120 #define CONFIG_SYS_HZ 1000
122 /* Physical Memory Map */
123 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
125 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
126 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
127 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
129 #define CONFIG_SYS_INIT_SP_OFFSET \
130 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
131 #define CONFIG_SYS_INIT_SP_ADDR \
132 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
134 /* SPI Flash support */
136 /* FLASH and environment organization */
139 #ifdef CONFIG_FSL_USDHC
140 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
142 #define CONFIG_SYS_FSL_USDHC_NUM 2
143 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
147 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
148 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
149 #define CONFIG_MXC_USB_FLAGS 0
150 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
152 /* Uncomment to enable iMX thermal driver support */
153 /*#define CONFIG_IMX_THERMAL*/
156 #include "imx7_spl.h"
158 #endif /* __CONFIG_H */