2 * Copyright (C) 2015 CompuLab, Ltd.
4 * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __CL_SOM_IMX7_CONFIG_H
10 #define __CL_SOM_IMX7_CONFIG_H
12 #include "mx7_common.h"
14 #define CONFIG_DBG_MONITOR
16 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
18 /* Size of malloc() pool */
19 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
21 #define CONFIG_BOARD_LATE_INIT
23 /* Uncomment to enable secure boot support */
24 /* #define CONFIG_SECURE_BOOT */
25 #define CONFIG_CSF_SIZE 0x4000
28 #define CONFIG_FEC_MXC
30 #define CONFIG_FEC_XCV_TYPE RGMII
31 #define CONFIG_ETHPRIME "FEC"
32 #define CONFIG_FEC_MXC_PHYADDR 0
35 #define CONFIG_PHY_ATHEROS
37 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR
41 #define CONFIG_POWER_I2C
42 #define CONFIG_POWER_PFUZE3000
43 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
45 #undef CONFIG_BOOTM_NETBSD
46 #undef CONFIG_BOOTM_PLAN9
47 #undef CONFIG_BOOTM_RTEMS
50 #define CONFIG_SYS_I2C
51 #define CONFIG_SYS_I2C_MXC
52 #define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */
53 #define CONFIG_SYS_I2C_SPEED 100000
54 #define SYS_I2C_BUS_SOM 0
56 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
57 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
58 #define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM
60 #define CONFIG_PCA953X
61 #define CONFIG_CMD_PCA953X
62 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
63 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
65 #undef CONFIG_SYS_AUTOLOAD
66 #undef CONFIG_EXTRA_ENV_SETTINGS
67 #undef CONFIG_BOOTCOMMAND
68 #undef CONFIG_BOOTDELAY
70 #define CONFIG_BOOTDELAY 3
71 #define CONFIG_SYS_AUTOLOAD "no"
73 #define CONFIG_EXTRA_ENV_SETTINGS \
76 "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \
77 "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \
78 "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\0" \
79 "bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\0" \
80 "storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\0" \
83 "fdt_high=0xffffffff\0" \
84 "initrd_high=0xffffffff\0" \
85 "fdtfile=imx7d-sbc-imx7.dtb\0" \
86 "fdtaddr=0x83000000\0" \
87 "mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \
88 "usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \
89 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
90 "usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \
91 "doboot=bootz ${loadaddr} - ${fdtaddr}\0" \
92 "mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \
93 "mmcargs=setenv bootargs console=${console},${baudrate} " \
94 "root=/dev/mmcblk${mmcblk}p2 rootwait rw\0" \
96 "if run mmc_config; then " \
97 "setenv storagetype mmc;" \
98 "setenv storagedev ${mmcdev}:${mmcpart};" \
99 "if run loadscript; then " \
104 "if run mmc_config; then " \
105 "setenv storagetype mmc;" \
106 "setenv storagedev ${mmcdev}:${mmcpart};" \
107 "if run loadkernel; then " \
108 "if run loadfdt; then " \
109 "run storagebootcmd;" \
113 "sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; " \
114 "run mmcbootscript\0" \
115 "usbbootscript=setenv usbdev ${usbdev_def}; " \
116 "setenv storagetype usb;" \
117 "setenv storagedev ${usbdev}:${usbpart};" \
118 "if run loadscript; then " \
121 "sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\0" \
122 "emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \
123 "emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \
125 #define CONFIG_BOOTCOMMAND \
126 "echo SD boot attempt ...; run sdbootscript; run sdboot; " \
127 "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \
128 "echo USB boot attempt ...; run usbbootscript; "
130 #define CONFIG_SYS_MEMTEST_START 0x80000000
131 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
133 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
134 #define CONFIG_SYS_HZ 1000
136 /* Physical Memory Map */
137 #define CONFIG_NR_DRAM_BANKS 1
138 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
140 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
141 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
142 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
144 #define CONFIG_SYS_INIT_SP_OFFSET \
145 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
146 #define CONFIG_SYS_INIT_SP_ADDR \
147 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
149 /* SPI Flash support */
151 #define CONFIG_MXC_SPI
152 #define CONFIG_SF_DEFAULT_BUS 0
153 #define CONFIG_SF_DEFAULT_CS 0
154 #define CONFIG_SF_DEFAULT_SPEED 20000000
155 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
157 /* FLASH and environment organization */
158 #define CONFIG_ENV_SIZE SZ_8K
159 #define CONFIG_ENV_OFFSET (768 * 1024)
160 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
161 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
162 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
163 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
164 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
167 #define CONFIG_FSL_USDHC
168 #ifdef CONFIG_FSL_USDHC
169 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
171 #define CONFIG_SYS_FSL_USDHC_NUM 2
172 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
173 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
177 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
178 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
179 #define CONFIG_MXC_USB_FLAGS 0
180 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
182 /* Uncomment to enable iMX thermal driver support */
183 /*#define CONFIG_IMX_THERMAL*/
186 #include "imx7_spl.h"
187 #ifdef CONFIG_SPL_BUILD
188 #define CONFIG_SPL_SPI_LOAD
189 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
190 #endif /* CONFIG_SPL_BUILD */
192 #endif /* __CONFIG_H */