1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
9 #ifndef __CONFIG_CI20_H__
10 #define __CONFIG_CI20_H__
12 /* Ingenic JZ4780 clock configuration. */
13 #define CONFIG_SYS_MHZ 1200
14 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
16 /* Memory configuration */
17 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
18 #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
20 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
21 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
23 /* NS16550-ish UARTs */
24 #define CONFIG_SYS_NS16550_CLK 48000000
26 /* Ethernet: davicom DM9000 */
27 #define CONFIG_DM9000_BASE 0xb6000000
28 #define DM9000_IO CONFIG_DM9000_BASE
29 #define DM9000_DATA (CONFIG_DM9000_BASE + 2)
31 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
32 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
33 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
34 /* Boot argument buffer size */
36 /* Miscellaneous configuration options */
37 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
40 #define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
42 #define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00)
44 #define CONFIG_SPL_BSS_START_ADDR 0xf4004000
45 #define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */
47 #define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx"
49 #endif /* __CONFIG_CI20_H__ */