1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
4 * Copyright 2018 congatec AG
11 #include <linux/sizes.h>
12 #include <asm/arch/imx-regs.h>
14 #ifdef CONFIG_SPL_BUILD
15 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
16 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
20 #define CONFIG_SPL_STACK 0x013E000
21 #define CONFIG_SPL_BSS_START_ADDR 0x00128000
22 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
23 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
24 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
25 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000
26 #define CONFIG_MALLOC_F_ADDR 0x00120000
28 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
30 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
33 #define CONFIG_REMAKE_ELF
35 /* Flat Device Tree Definitions */
36 #define CONFIG_OF_BOARD_SETUP
38 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
39 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
40 #define USDHC1_BASE_ADDR 0x5B010000
41 #define USDHC2_BASE_ADDR 0x5B020000
42 #define USDHC3_BASE_ADDR 0x5B030000
46 "m4_0_image=m4_0.bin\0" \
47 "m4_1_image=m4_1.bin\0" \
48 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
49 "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
50 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
51 "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
53 #ifdef CONFIG_NAND_BOOT
54 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
56 #define MFG_NAND_PARTITION ""
58 #define FEC0_RESET IMX_GPIO_NR(2, 5)
59 #define FEC0_PDOMAIN "conn_enet0"
61 #define CONFIG_MFG_ENV_SETTINGS \
62 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
64 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
65 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
66 "g_mass_storage.iSerialNumber=\"\" "\
70 "initrd_addr=0x83800000\0" \
71 "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
73 /* Initial environment variables */
74 #define CONFIG_EXTRA_ENV_SETTINGS \
75 CONFIG_MFG_ENV_SETTINGS \
81 "fdt_addr=0x83000000\0" \
83 "fdt_file=imx8qm-cgt-qmx8.dtb\0" \
84 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
85 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
86 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
87 "mmcautodetect=yes\0" \
88 "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
89 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
90 "bootscript=echo Running bootscript from mmc ...; " \
92 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
93 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
94 "mmcboot=echo Booting from mmc ...; " \
96 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
97 "if run loadfdt; then " \
98 "booti ${loadaddr} - ${fdt_addr}; " \
100 "echo WARN: Cannot load the DT; " \
103 "echo wait for boot; " \
105 "netargs=setenv bootargs console=${console},${baudrate} " \
107 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
108 "netboot=echo Booting from net ...; " \
110 "if test ${ip_dyn} = yes; then " \
111 "setenv get_cmd dhcp; " \
113 "setenv get_cmd tftp; " \
115 "${get_cmd} ${loadaddr} ${image}; " \
116 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
117 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
118 "booti ${loadaddr} - ${fdt_addr}; " \
120 "echo WARN: Cannot load the DT; " \
126 #define CONFIG_BOOTCOMMAND \
127 "mmc dev ${mmcdev}; if mmc rescan; then " \
128 "if run loadbootscript; then " \
131 "if run loadimage; then " \
133 "else run netboot; " \
136 "else booti ${loadaddr} - ${fdt_addr}; fi"
138 /* Link Definitions */
140 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
142 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
144 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
145 #define CONFIG_SYS_FSL_USDHC_NUM 3
147 #define CONFIG_SYS_SDRAM_BASE 0x80000000
148 #define PHYS_SDRAM_1 0x80000000
149 #define PHYS_SDRAM_2 0x880000000
150 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
151 #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
153 /* Generic Timer Definitions */
154 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
157 #define CONFIG_FEC_MXC_PHYADDR -1
158 #define CONFIG_FEC_XCV_TYPE RGMII
159 #define FEC_QUIRK_ENET_MAC
161 #endif /* __CGTQMX8_H */