include/configs/cgtqmx8.h

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  * Copyright 2018 congatec AG
   5  *
   6  */
   7
   8 #ifndef __CGTQMX8_H
   9 #define __CGTQMX8_H
  10
  11 #include <linux/sizes.h>
  12 #include <asm/arch/imx-regs.h>
  13
  14 #ifdef CONFIG_SPL_BUILD
  15 #define CONFIG_SPL_MAX_SIZE                             (124 * 1024)
  16 #define CONFIG_SYS_MONITOR_LEN                          (1024 * 1024)
  17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0x800
  19
  20 #define CONFIG_SPL_STACK                0x013E000
  21 #define CONFIG_SPL_BSS_START_ADDR       0x00128000
  22 #define CONFIG_SPL_BSS_MAX_SIZE         0x1000  /* 4 KB */
  23 #define CONFIG_SYS_SPL_MALLOC_START     0x00120000
  24 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x3000  /* 12 KB */
  25 #define CONFIG_SERIAL_LPUART_BASE       0x5a060000
  26 #define CONFIG_MALLOC_F_ADDR            0x00120000
  27
  28 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
  29
  30 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  31 #endif
  32
  33 #define CONFIG_REMAKE_ELF
  34
  35 /* Flat Device Tree Definitions */
  36 #define CONFIG_OF_BOARD_SETUP
  37
  38 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
  39 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
  40 #define USDHC1_BASE_ADDR                0x5B010000
  41 #define USDHC2_BASE_ADDR                0x5B020000
  42 #define USDHC3_BASE_ADDR                0x5B030000
  43
  44 /* Boot M4 */
  45 #define M4_BOOT_ENV \
  46         "m4_0_image=m4_0.bin\0" \
  47         "m4_1_image=m4_1.bin\0" \
  48         "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
  49         "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
  50         "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  51         "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
  52
  53 #ifdef CONFIG_NAND_BOOT
  54 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
  55 #else
  56 #define MFG_NAND_PARTITION ""
  57 #endif
  58 #define FEC0_RESET IMX_GPIO_NR(2, 5)
  59 #define FEC0_PDOMAIN "conn_enet0"
  60
  61 #define CONFIG_MFG_ENV_SETTINGS \
  62         "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  63                 "rdinit=/linuxrc " \
  64                 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  65                 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  66                 "g_mass_storage.iSerialNumber=\"\" "\
  67                 MFG_NAND_PARTITION \
  68                 "clk_ignore_unused "\
  69                 "\0" \
  70         "initrd_addr=0x83800000\0" \
  71         "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  72
  73 /* Initial environment variables */
  74 #define CONFIG_EXTRA_ENV_SETTINGS               \
  75         CONFIG_MFG_ENV_SETTINGS \
  76         M4_BOOT_ENV \
  77         "script=boot.scr\0" \
  78         "image=Image\0" \
  79         "panel=NULL\0" \
  80         "console=ttyLP0\0" \
  81         "fdt_addr=0x83000000\0"                 \
  82         "boot_fdt=try\0" \
  83         "fdt_file=imx8qm-cgt-qmx8.dtb\0" \
  84         "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
  85         "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  86         "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  87         "mmcautodetect=yes\0" \
  88         "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
  89         "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  90         "bootscript=echo Running bootscript from mmc ...; " \
  91                 "source\0" \
  92         "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  93         "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  94         "mmcboot=echo Booting from mmc ...; " \
  95                 "run mmcargs; " \
  96                 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  97                         "if run loadfdt; then " \
  98                                 "booti ${loadaddr} - ${fdt_addr}; " \
  99                         "else " \
 100                                 "echo WARN: Cannot load the DT; " \
 101                         "fi; " \
 102                 "else " \
 103                         "echo wait for boot; " \
 104                 "fi;\0" \
 105         "netargs=setenv bootargs console=${console},${baudrate} " \
 106                 "root=/dev/nfs " \
 107                 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
 108         "netboot=echo Booting from net ...; " \
 109                 "run netargs;  " \
 110                 "if test ${ip_dyn} = yes; then " \
 111                         "setenv get_cmd dhcp; " \
 112                 "else " \
 113                         "setenv get_cmd tftp; " \
 114                 "fi; " \
 115                 "${get_cmd} ${loadaddr} ${image}; " \
 116                 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 117                         "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
 118                                 "booti ${loadaddr} - ${fdt_addr}; " \
 119                         "else " \
 120                                 "echo WARN: Cannot load the DT; " \
 121                         "fi; " \
 122                 "else " \
 123                         "booti; " \
 124                 "fi;\0"
 125
 126 /* Link Definitions */
 127
 128 #define CONFIG_SYS_INIT_SP_ADDR         0x80200000
 129
 130 #define CONFIG_SYS_MMC_IMG_LOAD_PART    1
 131
 132 #define CONFIG_MMCROOT                  "/dev/mmcblk1p2"  /* USDHC2 */
 133 #define CONFIG_SYS_FSL_USDHC_NUM        3
 134
 135 #define CONFIG_SYS_SDRAM_BASE           0x80000000
 136 #define PHYS_SDRAM_1                    0x80000000
 137 #define PHYS_SDRAM_2                    0x880000000
 138 #define PHYS_SDRAM_1_SIZE               0x80000000      /* 2 GB */
 139 #define PHYS_SDRAM_2_SIZE               0x100000000     /* 4 GB */
 140
 141 /* Generic Timer Definitions */
 142 #define COUNTER_FREQUENCY               8000000 /* 8MHz */
 143
 144 /* Networking */
 145 #define CONFIG_FEC_MXC_PHYADDR          -1
 146 #define CONFIG_FEC_XCV_TYPE             RGMII
 147 #define FEC_QUIRK_ENET_MAC
 148
 149 #endif /* __CGTQMX8_H */