1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
4 * Copyright 2018 congatec AG
11 #include <linux/sizes.h>
12 #include <asm/arch/imx-regs.h>
14 #ifdef CONFIG_SPL_BUILD
15 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
16 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
20 #define CONFIG_SPL_STACK 0x013E000
21 #define CONFIG_SPL_BSS_START_ADDR 0x00128000
22 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
23 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
24 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
25 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000
26 #define CONFIG_MALLOC_F_ADDR 0x00120000
28 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
30 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
33 #define CONFIG_REMAKE_ELF
35 /* Flat Device Tree Definitions */
36 #define CONFIG_OF_BOARD_SETUP
38 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
39 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
40 #define USDHC1_BASE_ADDR 0x5B010000
41 #define USDHC2_BASE_ADDR 0x5B020000
42 #define USDHC3_BASE_ADDR 0x5B030000
44 #define CONFIG_ENV_OVERWRITE
48 "m4_0_image=m4_0.bin\0" \
49 "m4_1_image=m4_1.bin\0" \
50 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
51 "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
52 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
53 "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
55 #ifdef CONFIG_NAND_BOOT
56 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
58 #define MFG_NAND_PARTITION ""
60 #define FEC0_RESET IMX_GPIO_NR(2, 5)
61 #define FEC0_PDOMAIN "conn_enet0"
63 #define CONFIG_MFG_ENV_SETTINGS \
64 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
66 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
67 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
68 "g_mass_storage.iSerialNumber=\"\" "\
72 "initrd_addr=0x83800000\0" \
73 "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
75 /* Initial environment variables */
76 #define CONFIG_EXTRA_ENV_SETTINGS \
77 CONFIG_MFG_ENV_SETTINGS \
83 "fdt_addr=0x83000000\0" \
85 "fdt_file=imx8qm-cgt-qmx8.dtb\0" \
86 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
87 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
88 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
89 "mmcautodetect=yes\0" \
90 "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
91 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
92 "bootscript=echo Running bootscript from mmc ...; " \
94 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
95 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
96 "mmcboot=echo Booting from mmc ...; " \
98 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
99 "if run loadfdt; then " \
100 "booti ${loadaddr} - ${fdt_addr}; " \
102 "echo WARN: Cannot load the DT; " \
105 "echo wait for boot; " \
107 "netargs=setenv bootargs console=${console},${baudrate} " \
109 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
110 "netboot=echo Booting from net ...; " \
112 "if test ${ip_dyn} = yes; then " \
113 "setenv get_cmd dhcp; " \
115 "setenv get_cmd tftp; " \
117 "${get_cmd} ${loadaddr} ${image}; " \
118 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
119 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
120 "booti ${loadaddr} - ${fdt_addr}; " \
122 "echo WARN: Cannot load the DT; " \
128 #define CONFIG_BOOTCOMMAND \
129 "mmc dev ${mmcdev}; if mmc rescan; then " \
130 "if run loadbootscript; then " \
133 "if run loadimage; then " \
135 "else run netboot; " \
138 "else booti ${loadaddr} - ${fdt_addr}; fi"
140 /* Link Definitions */
142 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
144 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
146 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
147 #define CONFIG_SYS_FSL_USDHC_NUM 3
149 #define CONFIG_SYS_SDRAM_BASE 0x80000000
150 #define PHYS_SDRAM_1 0x80000000
151 #define PHYS_SDRAM_2 0x880000000
152 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
153 #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
155 /* Generic Timer Definitions */
156 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
159 #define CONFIG_FEC_MXC_PHYADDR -1
160 #define CONFIG_FEC_XCV_TYPE RGMII
161 #define FEC_QUIRK_ENET_MAC
163 #endif /* __CGTQMX8_H */