1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
4 * Copyright 2018 congatec AG
11 #include <linux/sizes.h>
12 #include <asm/arch/imx-regs.h>
14 #ifdef CONFIG_SPL_BUILD
15 #define CONFIG_SPL_TEXT_BASE 0x0
16 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
17 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
19 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
21 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
22 #define CONFIG_SPL_STACK 0x013E000
23 #define CONFIG_SPL_BSS_START_ADDR 0x00128000
24 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
25 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
26 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
27 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000
28 #define CONFIG_MALLOC_F_ADDR 0x00120000
30 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
32 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
34 #define CONFIG_OF_EMBED
37 #define CONFIG_REMAKE_ELF
39 #define CONFIG_BOARD_EARLY_INIT_F
41 /* Flat Device Tree Definitions */
42 #define CONFIG_OF_BOARD_SETUP
44 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
45 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
46 #define USDHC1_BASE_ADDR 0x5B010000
47 #define USDHC2_BASE_ADDR 0x5B020000
48 #define USDHC3_BASE_ADDR 0x5B030000
49 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
51 #define CONFIG_ENV_OVERWRITE
55 "m4_0_image=m4_0.bin\0" \
56 "m4_1_image=m4_1.bin\0" \
57 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
58 "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
59 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
60 "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
62 #ifdef CONFIG_NAND_BOOT
63 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
65 #define MFG_NAND_PARTITION ""
67 #define FEC0_RESET IMX_GPIO_NR(2, 5)
68 #define FEC0_PDOMAIN "conn_enet0"
70 #define CONFIG_MFG_ENV_SETTINGS \
71 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
73 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
74 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
75 "g_mass_storage.iSerialNumber=\"\" "\
79 "initrd_addr=0x83800000\0" \
80 "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
82 /* Initial environment variables */
83 #define CONFIG_EXTRA_ENV_SETTINGS \
84 CONFIG_MFG_ENV_SETTINGS \
90 "fdt_addr=0x83000000\0" \
92 "fdt_file=imx8qm-cgt-qmx8.dtb\0" \
93 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
94 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
95 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
96 "mmcautodetect=yes\0" \
97 "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
98 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
99 "bootscript=echo Running bootscript from mmc ...; " \
101 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
102 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
103 "mmcboot=echo Booting from mmc ...; " \
105 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
106 "if run loadfdt; then " \
107 "booti ${loadaddr} - ${fdt_addr}; " \
109 "echo WARN: Cannot load the DT; " \
112 "echo wait for boot; " \
114 "netargs=setenv bootargs console=${console},${baudrate} " \
116 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
117 "netboot=echo Booting from net ...; " \
119 "if test ${ip_dyn} = yes; then " \
120 "setenv get_cmd dhcp; " \
122 "setenv get_cmd tftp; " \
124 "${get_cmd} ${loadaddr} ${image}; " \
125 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
126 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
127 "booti ${loadaddr} - ${fdt_addr}; " \
129 "echo WARN: Cannot load the DT; " \
135 #define CONFIG_BOOTCOMMAND \
136 "mmc dev ${mmcdev}; if mmc rescan; then " \
137 "if run loadbootscript; then " \
140 "if run loadimage; then " \
142 "else run netboot; " \
145 "else booti ${loadaddr} - ${fdt_addr}; fi"
147 /* Link Definitions */
149 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
151 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
153 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
154 #define CONFIG_SYS_FSL_USDHC_NUM 3
156 #define CONFIG_SYS_SDRAM_BASE 0x80000000
157 #define PHYS_SDRAM_1 0x80000000
158 #define PHYS_SDRAM_2 0x880000000
159 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
160 #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
163 #define CONFIG_BAUDRATE 115200
165 /* Generic Timer Definitions */
166 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
169 #define CONFIG_FEC_MXC_PHYADDR -1
170 #define CONFIG_FEC_XCV_TYPE RGMII
171 #define FEC_QUIRK_ENET_MAC
173 #endif /* __CGTQMX8_H */