3 * Congatec Conga-QEVAl board configuration file.
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
6 * Based on Freescale i.MX6Q Sabre Lite board configuration file.
7 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
8 * Leo Sartre, <lsartre@adeneo-embedded.com>
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __CONFIG_CGTQMX6EVAL_H
14 #define __CONFIG_CGTQMX6EVAL_H
16 #include "mx6_common.h"
18 #define CONFIG_MACH_TYPE 4122
21 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
22 #define CONFIG_SPL_SPI_LOAD
26 /* Size of malloc() pool */
27 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
29 #define CONFIG_BOARD_EARLY_INIT_F
30 #define CONFIG_BOARD_LATE_INIT
31 #define CONFIG_MISC_INIT_R
33 #define CONFIG_MXC_UART
34 #define CONFIG_MXC_UART_BASE UART2_BASE
37 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
40 #define CONFIG_SPI_FLASH
41 #define CONFIG_SPI_FLASH_STMICRO
42 #define CONFIG_SPI_FLASH_SST
43 #define CONFIG_MXC_SPI
44 #define CONFIG_SF_DEFAULT_BUS 0
45 #define CONFIG_SF_DEFAULT_SPEED 20000000
46 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
48 /* Miscellaneous commands */
49 #define CONFIG_CMD_BMODE
52 #define CONFIG_IMX_THERMAL
55 #define CONFIG_SYS_I2C
56 #define CONFIG_SYS_I2C_MXC
57 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
58 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
59 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
60 #define CONFIG_SYS_I2C_SPEED 100000
64 #define CONFIG_POWER_I2C
65 #define CONFIG_POWER_PFUZE100
66 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
69 #define CONFIG_USB_EHCI
70 #define CONFIG_USB_EHCI_MX6
71 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
72 #define CONFIG_USB_HOST_ETHER
73 #define CONFIG_USB_ETHER_ASIX
74 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
75 #define CONFIG_MXC_USB_FLAGS 0
76 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
77 #define CONFIG_USB_KEYBOARD
78 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
80 #define CONFIG_USBD_HS
82 #define CONFIG_USB_FUNCTION_MASS_STORAGE
84 #define CONFIG_USB_FUNCTION_FASTBOOT
85 #define CONFIG_CMD_FASTBOOT
86 #define CONFIG_ANDROID_BOOT_IMAGE
87 #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
88 #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
92 #define CONFIG_VIDEO_IPUV3
93 #define CONFIG_CFB_CONSOLE
94 #define CONFIG_VGA_AS_SINGLE_DEVICE
95 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
96 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
97 #define CONFIG_VIDEO_BMP_RLE8
98 #define CONFIG_SPLASH_SCREEN
99 #define CONFIG_SPLASH_SCREEN_ALIGN
100 #define CONFIG_BMP_16BPP
101 #define CONFIG_VIDEO_LOGO
102 #define CONFIG_VIDEO_BMP_LOGO
104 #define CONFIG_IPUV3_CLK 198000000
106 #define CONFIG_IPUV3_CLK 264000000
108 #define CONFIG_IMX_HDMI
111 #define CONFIG_CMD_SATA
112 #define CONFIG_DWC_AHSATA
113 #define CONFIG_SYS_SATA_MAX_DEVICE 1
114 #define CONFIG_DWC_AHSATA_PORT_ID 0
115 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
117 #define CONFIG_LIBATA
120 #define CONFIG_FEC_MXC
122 #define IMX_FEC_BASE ENET_BASE_ADDR
123 #define CONFIG_FEC_XCV_TYPE RGMII
124 #define CONFIG_ETHPRIME "FEC"
125 #define CONFIG_FEC_MXC_PHYADDR 6
126 #define CONFIG_PHYLIB
127 #define CONFIG_PHY_ATHEROS
129 /* Command definition */
131 #define CONFIG_MXC_UART_BASE UART2_BASE
132 #define CONFIG_CONSOLE_DEV "ttymxc1"
133 #define CONFIG_MMCROOT "/dev/mmcblk0p2"
134 #define CONFIG_SYS_MMC_ENV_DEV 0
136 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
137 #define CONFIG_EXTRA_ENV_SETTINGS \
138 "script=boot.scr\0" \
140 "fdtfile=undefined\0" \
141 "fdt_addr_r=0x18000000\0" \
144 "console=" CONFIG_CONSOLE_DEV "\0" \
145 "dfuspi=dfu 0 sf 0:0:10000000:0\0" \
146 "dfu_alt_info_spl=spl raw 0x400\0" \
147 "dfu_alt_info_img=u-boot raw 0x10000\0" \
148 "dfu_alt_info=spl raw 0x400\0" \
149 "bootm_size=0x10000000\0" \
150 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
152 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
153 "update_sd_firmware=" \
154 "if test ${ip_dyn} = yes; then " \
155 "setenv get_cmd dhcp; " \
157 "setenv get_cmd tftp; " \
159 "if mmc dev ${mmcdev}; then " \
160 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
161 "setexpr fw_sz ${filesize} / 0x200; " \
162 "setexpr fw_sz ${fw_sz} + 1; " \
163 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
166 "mmcargs=setenv bootargs console=${console},${baudrate} " \
167 "root=${mmcroot}\0" \
169 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
170 "bootscript=echo Running bootscript from mmc ...; " \
172 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
173 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
174 "mmcboot=echo Booting from mmc ...; " \
176 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
177 "if run loadfdt; then " \
178 "bootz ${loadaddr} - ${fdt_addr_r}; " \
180 "if test ${boot_fdt} = try; then " \
183 "echo WARN: Cannot load the DT; " \
190 "if test $board_rev = MX6Q ; then " \
191 "setenv fdtfile imx6q-qmx6.dtb; fi; " \
192 "if test $board_rev = MX6DL ; then " \
193 "setenv fdtfile imx6dl-qmx6.dtb; fi; " \
194 "if test $fdtfile = undefined; then " \
195 "echo WARNING: Could not determine dtb to use; fi; \0" \
196 "netargs=setenv bootargs console=${console},${baudrate} " \
198 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
199 "netboot=echo Booting from net ...; " \
201 "if test ${ip_dyn} = yes; then " \
202 "setenv get_cmd dhcp; " \
204 "setenv get_cmd tftp; " \
206 "${get_cmd} ${image}; " \
207 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
208 "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
209 "bootz ${loadaddr} - ${fdt_addr_r}; " \
211 "if test ${boot_fdt} = try; then " \
214 "echo WARN: Cannot load the DT; " \
220 "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\
222 #define CONFIG_BOOTCOMMAND \
225 "mmc dev ${mmcdev};" \
226 "if mmc rescan; then " \
227 "if run loadbootscript; then " \
230 "if run loadimage; then " \
232 "else run netboot; " \
235 "else run netboot; fi"
237 #define CONFIG_SYS_MEMTEST_START 0x10000000
238 #define CONFIG_SYS_MEMTEST_END 0x10010000
239 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
241 /* Physical Memory Map */
242 #define CONFIG_NR_DRAM_BANKS 1
243 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
245 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
246 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
247 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
249 #define CONFIG_SYS_INIT_SP_OFFSET \
250 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
251 #define CONFIG_SYS_INIT_SP_ADDR \
252 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
254 /* Environment organization */
255 #if defined (CONFIG_ENV_IS_IN_MMC)
256 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
257 #define CONFIG_SYS_MMC_ENV_DEV 0
260 #define CONFIG_ENV_SIZE (8 * 1024)
262 #define CONFIG_ENV_IS_IN_SPI_FLASH
263 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
264 #define CONFIG_ENV_OFFSET (768 * 1024)
265 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
266 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
267 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
268 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
269 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
272 #endif /* __CONFIG_CGTQMX6EVAL_H */