3 * Congatec Conga-QEVAl board configuration file.
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
6 * Based on Freescale i.MX6Q Sabre Lite board configuration file.
7 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
8 * Leo Sartre, <lsartre@adeneo-embedded.com>
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __CONFIG_CGTQMX6EVAL_H
14 #define __CONFIG_CGTQMX6EVAL_H
16 #include "mx6_common.h"
18 #define CONFIG_MACH_TYPE 4122
21 #define CONFIG_SPL_LIBCOMMON_SUPPORT
22 #define CONFIG_SPL_MMC_SUPPORT
23 #define CONFIG_SPL_SPI_SUPPORT
24 #define CONFIG_SPL_SPI_FLASH_SUPPORT
25 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
26 #define CONFIG_SPL_SPI_LOAD
30 /* Size of malloc() pool */
31 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
33 #define CONFIG_BOARD_EARLY_INIT_F
34 #define CONFIG_BOARD_LATE_INIT
35 #define CONFIG_MISC_INIT_R
37 #define CONFIG_MXC_UART
38 #define CONFIG_MXC_UART_BASE UART2_BASE
41 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
44 #define CONFIG_SPI_FLASH
45 #define CONFIG_SPI_FLASH_STMICRO
46 #define CONFIG_SPI_FLASH_SST
47 #define CONFIG_MXC_SPI
48 #define CONFIG_SF_DEFAULT_BUS 0
49 #define CONFIG_SF_DEFAULT_SPEED 20000000
50 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
52 /* Miscellaneous commands */
53 #define CONFIG_CMD_BMODE
56 #define CONFIG_IMX_THERMAL
59 #define CONFIG_SYS_I2C
60 #define CONFIG_SYS_I2C_MXC
61 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
62 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
63 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
64 #define CONFIG_SYS_I2C_SPEED 100000
68 #define CONFIG_POWER_I2C
69 #define CONFIG_POWER_PFUZE100
70 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
73 #define CONFIG_USB_EHCI
74 #define CONFIG_USB_EHCI_MX6
75 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
76 #define CONFIG_USB_HOST_ETHER
77 #define CONFIG_USB_ETHER_ASIX
78 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
79 #define CONFIG_MXC_USB_FLAGS 0
80 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
81 #define CONFIG_USB_KEYBOARD
82 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
84 #define CONFIG_USBD_HS
86 #define CONFIG_USB_FUNCTION_MASS_STORAGE
88 /* USB Device Firmware Update support */
89 #define CONFIG_USB_FUNCTION_DFU
90 #define CONFIG_DFU_MMC
93 #define CONFIG_USB_FUNCTION_FASTBOOT
94 #define CONFIG_CMD_FASTBOOT
95 #define CONFIG_ANDROID_BOOT_IMAGE
96 #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
97 #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
101 #define CONFIG_VIDEO_IPUV3
102 #define CONFIG_CFB_CONSOLE
103 #define CONFIG_VGA_AS_SINGLE_DEVICE
104 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
105 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
106 #define CONFIG_VIDEO_BMP_RLE8
107 #define CONFIG_SPLASH_SCREEN
108 #define CONFIG_SPLASH_SCREEN_ALIGN
109 #define CONFIG_BMP_16BPP
110 #define CONFIG_VIDEO_LOGO
111 #define CONFIG_VIDEO_BMP_LOGO
113 #define CONFIG_IPUV3_CLK 198000000
115 #define CONFIG_IPUV3_CLK 264000000
117 #define CONFIG_IMX_HDMI
120 #define CONFIG_CMD_SATA
121 #define CONFIG_DWC_AHSATA
122 #define CONFIG_SYS_SATA_MAX_DEVICE 1
123 #define CONFIG_DWC_AHSATA_PORT_ID 0
124 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
126 #define CONFIG_LIBATA
129 #define CONFIG_FEC_MXC
131 #define IMX_FEC_BASE ENET_BASE_ADDR
132 #define CONFIG_FEC_XCV_TYPE RGMII
133 #define CONFIG_ETHPRIME "FEC"
134 #define CONFIG_FEC_MXC_PHYADDR 6
135 #define CONFIG_PHYLIB
136 #define CONFIG_PHY_ATHEROS
138 /* Command definition */
140 #define CONFIG_MXC_UART_BASE UART2_BASE
141 #define CONFIG_CONSOLE_DEV "ttymxc1"
142 #define CONFIG_MMCROOT "/dev/mmcblk0p2"
143 #define CONFIG_SYS_MMC_ENV_DEV 0
145 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
146 #define CONFIG_EXTRA_ENV_SETTINGS \
147 "script=boot.scr\0" \
149 "fdtfile=undefined\0" \
150 "fdt_addr_r=0x18000000\0" \
153 "console=" CONFIG_CONSOLE_DEV "\0" \
154 "dfuspi=dfu 0 sf 0:0:10000000:0\0" \
155 "dfu_alt_info_spl=spl raw 0x400\0" \
156 "dfu_alt_info_img=u-boot raw 0x10000\0" \
157 "dfu_alt_info=spl raw 0x400\0" \
158 "bootm_size=0x10000000\0" \
159 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
161 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
162 "update_sd_firmware=" \
163 "if test ${ip_dyn} = yes; then " \
164 "setenv get_cmd dhcp; " \
166 "setenv get_cmd tftp; " \
168 "if mmc dev ${mmcdev}; then " \
169 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
170 "setexpr fw_sz ${filesize} / 0x200; " \
171 "setexpr fw_sz ${fw_sz} + 1; " \
172 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
175 "mmcargs=setenv bootargs console=${console},${baudrate} " \
176 "root=${mmcroot}\0" \
178 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
179 "bootscript=echo Running bootscript from mmc ...; " \
181 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
182 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
183 "mmcboot=echo Booting from mmc ...; " \
185 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
186 "if run loadfdt; then " \
187 "bootz ${loadaddr} - ${fdt_addr_r}; " \
189 "if test ${boot_fdt} = try; then " \
192 "echo WARN: Cannot load the DT; " \
199 "if test $board_rev = MX6Q ; then " \
200 "setenv fdtfile imx6q-qmx6.dtb; fi; " \
201 "if test $board_rev = MX6DL ; then " \
202 "setenv fdtfile imx6dl-qmx6.dtb; fi; " \
203 "if test $fdtfile = undefined; then " \
204 "echo WARNING: Could not determine dtb to use; fi; \0" \
205 "netargs=setenv bootargs console=${console},${baudrate} " \
207 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
208 "netboot=echo Booting from net ...; " \
210 "if test ${ip_dyn} = yes; then " \
211 "setenv get_cmd dhcp; " \
213 "setenv get_cmd tftp; " \
215 "${get_cmd} ${image}; " \
216 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
217 "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
218 "bootz ${loadaddr} - ${fdt_addr_r}; " \
220 "if test ${boot_fdt} = try; then " \
223 "echo WARN: Cannot load the DT; " \
229 "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\
231 #define CONFIG_BOOTCOMMAND \
234 "mmc dev ${mmcdev};" \
235 "if mmc rescan; then " \
236 "if run loadbootscript; then " \
239 "if run loadimage; then " \
241 "else run netboot; " \
244 "else run netboot; fi"
246 #define CONFIG_SYS_MEMTEST_START 0x10000000
247 #define CONFIG_SYS_MEMTEST_END 0x10010000
248 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
250 /* Physical Memory Map */
251 #define CONFIG_NR_DRAM_BANKS 1
252 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
254 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
255 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
256 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
258 #define CONFIG_SYS_INIT_SP_OFFSET \
259 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
260 #define CONFIG_SYS_INIT_SP_ADDR \
261 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
263 /* Environment organization */
264 #if defined (CONFIG_ENV_IS_IN_MMC)
265 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
266 #define CONFIG_SYS_MMC_ENV_DEV 0
269 #define CONFIG_ENV_SIZE (8 * 1024)
271 #define CONFIG_ENV_IS_IN_SPI_FLASH
272 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
273 #define CONFIG_ENV_OFFSET (768 * 1024)
274 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
275 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
276 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
277 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
278 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
281 #endif /* __CONFIG_CGTQMX6EVAL_H */