3 * Congatec Conga-QEVAl board configuration file.
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
6 * Based on Freescale i.MX6Q Sabre Lite board configuration file.
7 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
8 * Leo Sartre, <lsartre@adeneo-embedded.com>
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __CONFIG_CGTQMX6EVAL_H
14 #define __CONFIG_CGTQMX6EVAL_H
16 #include "mx6_common.h"
18 #define CONFIG_MACH_TYPE 4122
21 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
22 #define CONFIG_SPL_SPI_LOAD
26 /* Size of malloc() pool */
27 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
29 #define CONFIG_MISC_INIT_R
31 #define CONFIG_MXC_UART
32 #define CONFIG_MXC_UART_BASE UART2_BASE
35 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
38 #define CONFIG_SPI_FLASH
39 #define CONFIG_SPI_FLASH_STMICRO
40 #define CONFIG_SPI_FLASH_SST
41 #define CONFIG_MXC_SPI
42 #define CONFIG_SF_DEFAULT_BUS 0
43 #define CONFIG_SF_DEFAULT_SPEED 20000000
44 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
47 #define CONFIG_IMX_THERMAL
50 #define CONFIG_SYS_I2C
51 #define CONFIG_SYS_I2C_MXC
52 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
53 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
54 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
55 #define CONFIG_SYS_I2C_SPEED 100000
59 #define CONFIG_POWER_I2C
60 #define CONFIG_POWER_PFUZE100
61 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
64 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
65 #define CONFIG_USB_HOST_ETHER
66 #define CONFIG_USB_ETHER_ASIX
67 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
68 #define CONFIG_MXC_USB_FLAGS 0
69 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
70 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
72 #define CONFIG_USBD_HS
74 #define CONFIG_USB_FUNCTION_MASS_STORAGE
76 #define CONFIG_USB_FUNCTION_FASTBOOT
77 #define CONFIG_CMD_FASTBOOT
78 #define CONFIG_ANDROID_BOOT_IMAGE
79 #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
80 #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
83 #define CONFIG_VIDEO_IPUV3
84 #define CONFIG_VIDEO_BMP_RLE8
85 #define CONFIG_SPLASH_SCREEN
86 #define CONFIG_SPLASH_SCREEN_ALIGN
87 #define CONFIG_BMP_16BPP
88 #define CONFIG_VIDEO_LOGO
89 #define CONFIG_VIDEO_BMP_LOGO
91 #define CONFIG_IPUV3_CLK 198000000
93 #define CONFIG_IPUV3_CLK 264000000
95 #define CONFIG_IMX_HDMI
98 #define CONFIG_CMD_SATA
99 #define CONFIG_DWC_AHSATA
100 #define CONFIG_SYS_SATA_MAX_DEVICE 1
101 #define CONFIG_DWC_AHSATA_PORT_ID 0
102 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
104 #define CONFIG_LIBATA
107 #define CONFIG_FEC_MXC
109 #define IMX_FEC_BASE ENET_BASE_ADDR
110 #define CONFIG_FEC_XCV_TYPE RGMII
111 #define CONFIG_ETHPRIME "FEC"
112 #define CONFIG_FEC_MXC_PHYADDR 6
113 #define CONFIG_PHYLIB
114 #define CONFIG_PHY_ATHEROS
116 /* Command definition */
118 #define CONFIG_MXC_UART_BASE UART2_BASE
119 #define CONSOLE_DEV "ttymxc1"
120 #define CONFIG_MMCROOT "/dev/mmcblk0p2"
121 #define CONFIG_SYS_MMC_ENV_DEV 0
123 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
124 #define CONFIG_EXTRA_ENV_SETTINGS \
125 "script=boot.scr\0" \
127 "fdtfile=undefined\0" \
128 "fdt_addr_r=0x18000000\0" \
131 "console=" CONSOLE_DEV "\0" \
132 "dfuspi=dfu 0 sf 0:0:10000000:0\0" \
133 "dfu_alt_info_spl=spl raw 0x400\0" \
134 "dfu_alt_info_img=u-boot raw 0x10000\0" \
135 "dfu_alt_info=spl raw 0x400\0" \
136 "bootm_size=0x10000000\0" \
137 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
139 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
140 "update_sd_firmware=" \
141 "if test ${ip_dyn} = yes; then " \
142 "setenv get_cmd dhcp; " \
144 "setenv get_cmd tftp; " \
146 "if mmc dev ${mmcdev}; then " \
147 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
148 "setexpr fw_sz ${filesize} / 0x200; " \
149 "setexpr fw_sz ${fw_sz} + 1; " \
150 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
153 "mmcargs=setenv bootargs console=${console},${baudrate} " \
154 "root=${mmcroot}\0" \
156 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
157 "bootscript=echo Running bootscript from mmc ...; " \
159 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
160 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
161 "mmcboot=echo Booting from mmc ...; " \
163 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
164 "if run loadfdt; then " \
165 "bootz ${loadaddr} - ${fdt_addr_r}; " \
167 "if test ${boot_fdt} = try; then " \
170 "echo WARN: Cannot load the DT; " \
177 "if test $board_rev = MX6Q ; then " \
178 "setenv fdtfile imx6q-qmx6.dtb; fi; " \
179 "if test $board_rev = MX6DL ; then " \
180 "setenv fdtfile imx6dl-qmx6.dtb; fi; " \
181 "if test $fdtfile = undefined; then " \
182 "echo WARNING: Could not determine dtb to use; fi; \0" \
183 "netargs=setenv bootargs console=${console},${baudrate} " \
185 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
186 "netboot=echo Booting from net ...; " \
188 "if test ${ip_dyn} = yes; then " \
189 "setenv get_cmd dhcp; " \
191 "setenv get_cmd tftp; " \
193 "${get_cmd} ${image}; " \
194 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
195 "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
196 "bootz ${loadaddr} - ${fdt_addr_r}; " \
198 "if test ${boot_fdt} = try; then " \
201 "echo WARN: Cannot load the DT; " \
207 "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\
209 #define CONFIG_BOOTCOMMAND \
212 "mmc dev ${mmcdev};" \
213 "if mmc rescan; then " \
214 "if run loadbootscript; then " \
217 "if run loadimage; then " \
219 "else run netboot; " \
222 "else run netboot; fi"
224 #define CONFIG_SYS_MEMTEST_START 0x10000000
225 #define CONFIG_SYS_MEMTEST_END 0x10010000
226 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
228 /* Physical Memory Map */
229 #define CONFIG_NR_DRAM_BANKS 1
230 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
232 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
233 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
234 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
236 #define CONFIG_SYS_INIT_SP_OFFSET \
237 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
238 #define CONFIG_SYS_INIT_SP_ADDR \
239 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
241 /* Environment organization */
242 #if defined (CONFIG_ENV_IS_IN_MMC)
243 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
244 #define CONFIG_SYS_MMC_ENV_DEV 0
247 #define CONFIG_ENV_SIZE (8 * 1024)
249 #define CONFIG_ENV_IS_IN_SPI_FLASH
250 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
251 #define CONFIG_ENV_OFFSET (768 * 1024)
252 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
253 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
254 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
255 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
256 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
259 #endif /* __CONFIG_CGTQMX6EVAL_H */