1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
4 * Copyright 2019 Siemens AG
7 #ifndef __IMX8X_CAPRICORN_H
8 #define __IMX8X_CAPRICORN_H
10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h>
13 #include "siemens-env-common.h"
16 #ifdef CONFIG_SPL_BUILD
18 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
20 #define CONFIG_MALLOC_F_ADDR 0x00120000
22 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
23 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
25 #endif /* CONFIG_SPL_BUILD */
27 #define CONFIG_FACTORYSET
29 /* ENET1 connects to base board and MUX with ESAI */
30 #define CONFIG_FEC_ENET_DEV 1
31 #define CONFIG_FEC_MXC_PHYADDR 0x0
33 /* I2C Configuration */
34 #ifndef CONFIG_SPL_BUILD
36 #define EEPROM_I2C_BUS 0 /* I2C0 */
37 #define EEPROM_I2C_ADDR 0x50
39 #define PCA9552_1_I2C_BUS 1 /* I2C1 */
40 #define PCA9552_1_I2C_ADDR 0x60
41 #endif /* !CONFIG_SPL_BUILD */
44 #ifdef CONFIG_AHAB_BOOT
45 #define AHAB_ENV "sec_boot=yes\0"
47 #define AHAB_ENV "sec_boot=no\0"
50 #define MFG_ENV_SETTINGS_DEFAULT \
51 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
56 "bootcmd_mfg=run mfgtool_args;" \
57 "if iminfo ${initrd_addr}; then " \
58 "if test ${tee} = yes; then " \
59 "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
61 "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
64 "echo \"Run fastboot ...\"; fastboot 0; " \
69 "m4_0_image=m4_0.bin\0" \
70 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
71 "${loadaddr} ${m4_0_image}\0" \
72 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
74 #define CONFIG_MFG_ENV_SETTINGS \
75 MFG_ENV_SETTINGS_DEFAULT \
76 "initrd_addr=0x83100000\0" \
77 "initrd_high=0xffffffffffffffff\0" \
80 /* Initial environment variables */
81 #define CONFIG_EXTRA_ENV_SETTINGS \
82 CONFIG_MFG_ENV_SETTINGS \
90 "fdt_addr=0x83000000\0" \
91 "fdt_high=0xffffffffffffffff\0" \
92 "cntr_addr=0x88000000\0" \
93 "cntr_file=os_cntr_signed.bin\0" \
94 "initrd_addr=0x83800000\0" \
95 "initrd_high=0xffffffffffffffff\0" \
97 "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
98 "hostname=capricorn\0" \
102 /* Default location for tftp and bootm */
104 /* On CCP board, USDHC1 is for eMMC */
106 #define CONFIG_SYS_SDRAM_BASE 0x80000000
107 #define PHYS_SDRAM_1 0x80000000
108 #define PHYS_SDRAM_2 0x880000000
109 /* DDR3 board total DDR is 1 GB */
110 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
111 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
113 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
114 #define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
116 #endif /* __IMX8X_CAPRICORN_H */