1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
4 * Copyright 2019 Siemens AG
7 #ifndef __IMX8X_CAPRICORN_H
8 #define __IMX8X_CAPRICORN_H
10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h>
13 #include "siemens-env-common.h"
14 #include "siemens-ccp-common.h"
17 #ifdef CONFIG_SPL_BUILD
19 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
20 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
21 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
22 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
23 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
25 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
26 #define CONFIG_SPL_STACK 0x013E000
27 #define CONFIG_SPL_BSS_START_ADDR 0x00128000
28 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
29 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
30 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
31 #define CONFIG_MALLOC_F_ADDR 0x00120000
33 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
34 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
36 #endif /* CONFIG_SPL_BUILD */
38 #define CONFIG_FACTORYSET
40 #undef CONFIG_IDENT_STRING
41 #define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
43 #define CONFIG_REMAKE_ELF
46 #define CONFIG_FEC_XCV_TYPE RMII
47 #define FEC_QUIRK_ENET_MAC
49 /* ENET1 connects to base board and MUX with ESAI */
50 #define CONFIG_FEC_ENET_DEV 1
51 #define CONFIG_FEC_MXC_PHYADDR 0x0
52 #define CONFIG_ETHPRIME "eth1"
54 /* I2C Configuration */
55 #ifndef CONFIG_SPL_BUILD
56 #define CONFIG_SYS_I2C_SPEED 400000
58 #define EEPROM_I2C_BUS 0 /* I2C0 */
59 #define EEPROM_I2C_ADDR 0x50
61 #define PCA9552_1_I2C_BUS 1 /* I2C1 */
62 #define PCA9552_1_I2C_ADDR 0x60
63 #endif /* !CONFIG_SPL_BUILD */
66 #ifdef CONFIG_AHAB_BOOT
67 #define AHAB_ENV "sec_boot=yes\0"
69 #define AHAB_ENV "sec_boot=no\0"
72 #define MFG_ENV_SETTINGS_DEFAULT \
73 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
78 "bootcmd_mfg=run mfgtool_args;" \
79 "if iminfo ${initrd_addr}; then " \
80 "if test ${tee} = yes; then " \
81 "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
83 "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
86 "echo \"Run fastboot ...\"; fastboot 0; " \
91 "m4_0_image=m4_0.bin\0" \
92 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
93 "${loadaddr} ${m4_0_image}\0" \
94 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
96 #define CONFIG_MFG_ENV_SETTINGS \
97 MFG_ENV_SETTINGS_DEFAULT \
98 "initrd_addr=0x83100000\0" \
99 "initrd_high=0xffffffffffffffff\0" \
102 /* Initial environment variables */
103 #define CONFIG_EXTRA_ENV_SETTINGS \
104 CONFIG_MFG_ENV_SETTINGS \
108 "script=boot.scr\0" \
112 "fdt_addr=0x83000000\0" \
113 "fdt_high=0xffffffffffffffff\0" \
114 "cntr_addr=0x88000000\0" \
115 "cntr_file=os_cntr_signed.bin\0" \
116 "initrd_addr=0x83800000\0" \
117 "initrd_high=0xffffffffffffffff\0" \
119 "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
120 "hostname=capricorn\0" \
124 #define CONFIG_BOOTCOMMAND \
125 "if usrbutton; then " \
126 "run flash_self_test; " \
132 /* Default location for tftp and bootm */
133 #define CONFIG_LOADADDR 0x80280000
134 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
135 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
137 /* Environment organisation */
138 #define CONFIG_ENV_OVERWRITE
139 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1, eMMC */
140 #define CONFIG_SYS_MMC_ENV_PART 2 /* 2nd boot partition */
142 /* On CCP board, USDHC1 is for eMMC */
143 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
144 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
146 /* Size of malloc() pool */
147 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
149 #define CONFIG_SYS_SDRAM_BASE 0x80000000
150 #define PHYS_SDRAM_1 0x80000000
151 #define PHYS_SDRAM_2 0x880000000
152 /* DDR3 board total DDR is 1 GB */
153 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
154 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
156 /* Console buffer and boot args */
157 #define CONFIG_SYS_CBSIZE 2048
158 #define CONFIG_SYS_MAXARGS 64
159 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
161 /* Generic Timer Definitions */
162 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
164 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
165 #define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
167 #endif /* __IMX8X_CAPRICORN_H */