include/configs/capricorn-common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017-2018 NXP
   4  * Copyright 2019 Siemens AG
   5  */
   6
   7 #ifndef __IMX8X_CAPRICORN_H
   8 #define __IMX8X_CAPRICORN_H
   9
  10 #include <linux/sizes.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #include "siemens-env-common.h"
  14 #include "siemens-ccp-common.h"
  15
  16 /* SPL config */
  17 #ifdef CONFIG_SPL_BUILD
  18
  19 #define CONFIG_SPL_MAX_SIZE             (124 * 1024)
  20 #define CONFIG_SYS_MONITOR_LEN          (1024 * 1024)
  21 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  22 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0x800
  23 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION              0
  24
  25 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  26 #define CONFIG_SPL_STACK                0x013E000
  27 #define CONFIG_SPL_BSS_START_ADDR       0x00128000
  28 #define CONFIG_SPL_BSS_MAX_SIZE         0x1000  /* 4 KB */
  29 #define CONFIG_SYS_SPL_MALLOC_START     0x00120000
  30 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x3000  /* 12 KB */
  31 #define CONFIG_MALLOC_F_ADDR            0x00120000
  32
  33 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
  34 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  35
  36 #endif /* CONFIG_SPL_BUILD */
  37
  38 #define CONFIG_FACTORYSET
  39
  40 #undef CONFIG_IDENT_STRING
  41 #define CONFIG_IDENT_STRING             GENERATE_CCP_VERSION("01", "07")
  42
  43 #define CONFIG_REMAKE_ELF
  44
  45 /* Commands */
  46
  47 #undef CONFIG_BOOTM_NETBSD
  48
  49 /* ENET Config */
  50 #define CONFIG_FEC_XCV_TYPE             RMII
  51 #define FEC_QUIRK_ENET_MAC
  52
  53 /* ENET1 connects to base board and MUX with ESAI */
  54 #define CONFIG_FEC_ENET_DEV             1
  55 #define CONFIG_FEC_MXC_PHYADDR          0x0
  56 #define CONFIG_ETHPRIME                "eth1"
  57
  58 /* I2C Configuration */
  59 #ifndef CONFIG_SPL_BUILD
  60 #define CONFIG_SYS_I2C_SPEED    400000
  61 /* EEPROM */
  62 #define  EEPROM_I2C_BUS         0 /* I2C0 */
  63 #define  EEPROM_I2C_ADDR        0x50
  64 /* PCA9552 */
  65 #define  PCA9552_1_I2C_BUS      1 /* I2C1 */
  66 #define  PCA9552_1_I2C_ADDR     0x60
  67 #endif /* !CONFIG_SPL_BUILD */
  68
  69 /* AHAB */
  70 #ifdef CONFIG_AHAB_BOOT
  71 #define AHAB_ENV "sec_boot=yes\0"
  72 #else
  73 #define AHAB_ENV "sec_boot=no\0"
  74 #endif
  75
  76 #define MFG_ENV_SETTINGS_DEFAULT \
  77         "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  78                 "rdinit=/linuxrc " \
  79                 "clk_ignore_unused "\
  80                 "\0" \
  81         "kboot=booti\0"\
  82         "bootcmd_mfg=run mfgtool_args;" \
  83         "if iminfo ${initrd_addr}; then " \
  84         "if test ${tee} = yes; then " \
  85                 "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
  86         "else " \
  87                 "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
  88         "fi; " \
  89         "else " \
  90             "echo \"Run fastboot ...\"; fastboot 0; "  \
  91         "fi;\0"
  92
  93 /* Boot M4 */
  94 #define M4_BOOT_ENV \
  95         "m4_0_image=m4_0.bin\0" \
  96         "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
  97                         "${loadaddr} ${m4_0_image}\0" \
  98         "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  99
 100 #define CONFIG_MFG_ENV_SETTINGS \
 101         MFG_ENV_SETTINGS_DEFAULT \
 102         "initrd_addr=0x83100000\0" \
 103         "initrd_high=0xffffffffffffffff\0" \
 104         "emmc_dev=0\0"
 105
 106 /* Initial environment variables */
 107 #define CONFIG_EXTRA_ENV_SETTINGS \
 108         CONFIG_MFG_ENV_SETTINGS \
 109         M4_BOOT_ENV \
 110         AHAB_ENV \
 111         ENV_COMMON \
 112         "script=boot.scr\0" \
 113         "image=Image\0" \
 114         "panel=NULL\0" \
 115         "console=ttyLP2\0" \
 116         "fdt_addr=0x83000000\0" \
 117         "fdt_high=0xffffffffffffffff\0" \
 118         "cntr_addr=0x88000000\0" \
 119         "cntr_file=os_cntr_signed.bin\0" \
 120         "initrd_addr=0x83800000\0" \
 121         "initrd_high=0xffffffffffffffff\0" \
 122         "netdev=eth0\0" \
 123         "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
 124         "hostname=capricorn\0" \
 125         ENV_EMMC \
 126         ENV_NET
 127
 128 #define CONFIG_BOOTCOMMAND \
 129         "if usrbutton; then " \
 130                 "run flash_self_test; " \
 131                 "reset; " \
 132         "fi;" \
 133         "run flash_self;" \
 134         "reset;"
 135
 136 /* Default location for tftp and bootm */
 137 #define CONFIG_LOADADDR                 0x80280000
 138 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
 139 #define CONFIG_SYS_INIT_SP_ADDR         0x80200000
 140
 141 /* Environment organisation */
 142 #define CONFIG_ENV_OVERWRITE
 143 #define CONFIG_SYS_MMC_ENV_DEV          0       /* USDHC1, eMMC */
 144 #define CONFIG_SYS_MMC_ENV_PART         2       /* 2nd boot partition */
 145
 146 /* On CCP board, USDHC1 is for eMMC */
 147 #define CONFIG_MMCROOT                  "/dev/mmcblk0p2"  /* eMMC */
 148 #define CONFIG_SYS_MMC_IMG_LOAD_PART    1
 149
 150 /* Size of malloc() pool */
 151 #define CONFIG_SYS_MALLOC_LEN           ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
 152
 153 #define CONFIG_SYS_SDRAM_BASE           0x80000000
 154 #define PHYS_SDRAM_1                    0x80000000
 155 #define PHYS_SDRAM_2                    0x880000000
 156 /* DDR3 board total DDR is 1 GB */
 157 #define PHYS_SDRAM_1_SIZE               0x40000000      /* 1 GB */
 158 #define PHYS_SDRAM_2_SIZE               0x00000000      /* 0 GB */
 159
 160 /* Console buffer and boot args */
 161 #define CONFIG_SYS_CBSIZE               2048
 162 #define CONFIG_SYS_MAXARGS              64
 163 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 164
 165 /* Generic Timer Definitions */
 166 #define COUNTER_FREQUENCY               8000000 /* 8MHz */
 167
 168 #define BOOTAUX_RESERVED_MEM_BASE       0x88000000
 169 #define BOOTAUX_RESERVED_MEM_SIZE       SZ_128M /* Reserve from second 128MB */
 170
 171 #endif /* __IMX8X_CAPRICORN_H */