1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
4 * Copyright 2019 Siemens AG
7 #ifndef __IMX8X_CAPRICORN_H
8 #define __IMX8X_CAPRICORN_H
10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h>
13 #include "siemens-env-common.h"
14 #include "siemens-ccp-common.h"
17 #ifdef CONFIG_SPL_BUILD
19 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
20 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
21 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
22 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
24 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
25 #define CONFIG_SPL_STACK 0x013E000
26 #define CONFIG_SPL_BSS_START_ADDR 0x00128000
27 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
28 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
29 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
30 #define CONFIG_MALLOC_F_ADDR 0x00120000
32 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
33 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
35 #endif /* CONFIG_SPL_BUILD */
37 #define CONFIG_FACTORYSET
39 #undef CONFIG_IDENT_STRING
40 #define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
42 #define CONFIG_REMAKE_ELF
45 #define CONFIG_FEC_XCV_TYPE RMII
47 /* ENET1 connects to base board and MUX with ESAI */
48 #define CONFIG_FEC_ENET_DEV 1
49 #define CONFIG_FEC_MXC_PHYADDR 0x0
50 #define CONFIG_ETHPRIME "eth1"
52 /* I2C Configuration */
53 #ifndef CONFIG_SPL_BUILD
54 #define CONFIG_SYS_I2C_SPEED 400000
56 #define EEPROM_I2C_BUS 0 /* I2C0 */
57 #define EEPROM_I2C_ADDR 0x50
59 #define PCA9552_1_I2C_BUS 1 /* I2C1 */
60 #define PCA9552_1_I2C_ADDR 0x60
61 #endif /* !CONFIG_SPL_BUILD */
64 #ifdef CONFIG_AHAB_BOOT
65 #define AHAB_ENV "sec_boot=yes\0"
67 #define AHAB_ENV "sec_boot=no\0"
70 #define MFG_ENV_SETTINGS_DEFAULT \
71 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
76 "bootcmd_mfg=run mfgtool_args;" \
77 "if iminfo ${initrd_addr}; then " \
78 "if test ${tee} = yes; then " \
79 "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
81 "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
84 "echo \"Run fastboot ...\"; fastboot 0; " \
89 "m4_0_image=m4_0.bin\0" \
90 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
91 "${loadaddr} ${m4_0_image}\0" \
92 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
94 #define CONFIG_MFG_ENV_SETTINGS \
95 MFG_ENV_SETTINGS_DEFAULT \
96 "initrd_addr=0x83100000\0" \
97 "initrd_high=0xffffffffffffffff\0" \
100 /* Initial environment variables */
101 #define CONFIG_EXTRA_ENV_SETTINGS \
102 CONFIG_MFG_ENV_SETTINGS \
106 "script=boot.scr\0" \
110 "fdt_addr=0x83000000\0" \
111 "fdt_high=0xffffffffffffffff\0" \
112 "cntr_addr=0x88000000\0" \
113 "cntr_file=os_cntr_signed.bin\0" \
114 "initrd_addr=0x83800000\0" \
115 "initrd_high=0xffffffffffffffff\0" \
117 "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
118 "hostname=capricorn\0" \
122 #define CONFIG_BOOTCOMMAND \
123 "if usrbutton; then " \
124 "run flash_self_test; " \
130 /* Default location for tftp and bootm */
131 #define CONFIG_LOADADDR 0x80280000
132 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
133 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
135 /* On CCP board, USDHC1 is for eMMC */
136 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
137 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
139 /* Size of malloc() pool */
140 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
142 #define CONFIG_SYS_SDRAM_BASE 0x80000000
143 #define PHYS_SDRAM_1 0x80000000
144 #define PHYS_SDRAM_2 0x880000000
145 /* DDR3 board total DDR is 1 GB */
146 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
147 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
149 /* Console buffer and boot args */
150 #define CONFIG_SYS_CBSIZE 2048
151 #define CONFIG_SYS_MAXARGS 64
152 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
154 /* Generic Timer Definitions */
155 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
157 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
158 #define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
160 #endif /* __IMX8X_CAPRICORN_H */