include/configs/capricorn-common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017-2018 NXP
   4  * Copyright 2019 Siemens AG
   5  */
   6
   7 #ifndef __IMX8X_CAPRICORN_H
   8 #define __IMX8X_CAPRICORN_H
   9
  10 #include <linux/sizes.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #include "siemens-env-common.h"
  14
  15 /* SPL config */
  16 #ifdef CONFIG_SPL_BUILD
  17
  18 #define CONFIG_SPL_MAX_SIZE             (124 * 1024)
  19 #define CONFIG_SYS_MONITOR_LEN          (1024 * 1024)
  20
  21 #define CONFIG_SPL_STACK                0x013E000
  22 #define CONFIG_SPL_BSS_START_ADDR       0x00128000
  23 #define CONFIG_SPL_BSS_MAX_SIZE         0x1000  /* 4 KB */
  24 #define CONFIG_SYS_SPL_MALLOC_START     0x00120000
  25 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x3000  /* 12 KB */
  26 #define CONFIG_MALLOC_F_ADDR            0x00120000
  27
  28 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
  29 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  30
  31 #endif /* CONFIG_SPL_BUILD */
  32
  33 #define CONFIG_FACTORYSET
  34
  35 /* ENET Config */
  36 #define CONFIG_FEC_XCV_TYPE             RMII
  37
  38 /* ENET1 connects to base board and MUX with ESAI */
  39 #define CONFIG_FEC_ENET_DEV             1
  40 #define CONFIG_FEC_MXC_PHYADDR          0x0
  41 #define CONFIG_ETHPRIME                "eth1"
  42
  43 /* I2C Configuration */
  44 #ifndef CONFIG_SPL_BUILD
  45 /* EEPROM */
  46 #define  EEPROM_I2C_BUS         0 /* I2C0 */
  47 #define  EEPROM_I2C_ADDR        0x50
  48 /* PCA9552 */
  49 #define  PCA9552_1_I2C_BUS      1 /* I2C1 */
  50 #define  PCA9552_1_I2C_ADDR     0x60
  51 #endif /* !CONFIG_SPL_BUILD */
  52
  53 /* AHAB */
  54 #ifdef CONFIG_AHAB_BOOT
  55 #define AHAB_ENV "sec_boot=yes\0"
  56 #else
  57 #define AHAB_ENV "sec_boot=no\0"
  58 #endif
  59
  60 #define MFG_ENV_SETTINGS_DEFAULT \
  61         "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  62                 "rdinit=/linuxrc " \
  63                 "clk_ignore_unused "\
  64                 "\0" \
  65         "kboot=booti\0"\
  66         "bootcmd_mfg=run mfgtool_args;" \
  67         "if iminfo ${initrd_addr}; then " \
  68         "if test ${tee} = yes; then " \
  69                 "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
  70         "else " \
  71                 "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
  72         "fi; " \
  73         "else " \
  74             "echo \"Run fastboot ...\"; fastboot 0; "  \
  75         "fi;\0"
  76
  77 /* Boot M4 */
  78 #define M4_BOOT_ENV \
  79         "m4_0_image=m4_0.bin\0" \
  80         "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
  81                         "${loadaddr} ${m4_0_image}\0" \
  82         "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  83
  84 #define CONFIG_MFG_ENV_SETTINGS \
  85         MFG_ENV_SETTINGS_DEFAULT \
  86         "initrd_addr=0x83100000\0" \
  87         "initrd_high=0xffffffffffffffff\0" \
  88         "emmc_dev=0\0"
  89
  90 /* Initial environment variables */
  91 #define CONFIG_EXTRA_ENV_SETTINGS \
  92         CONFIG_MFG_ENV_SETTINGS \
  93         M4_BOOT_ENV \
  94         AHAB_ENV \
  95         ENV_COMMON \
  96         "script=boot.scr\0" \
  97         "image=Image\0" \
  98         "panel=NULL\0" \
  99         "console=ttyLP2\0" \
 100         "fdt_addr=0x83000000\0" \
 101         "fdt_high=0xffffffffffffffff\0" \
 102         "cntr_addr=0x88000000\0" \
 103         "cntr_file=os_cntr_signed.bin\0" \
 104         "initrd_addr=0x83800000\0" \
 105         "initrd_high=0xffffffffffffffff\0" \
 106         "netdev=eth0\0" \
 107         "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
 108         "hostname=capricorn\0" \
 109         ENV_EMMC \
 110         ENV_NET
 111
 112 /* Default location for tftp and bootm */
 113 #define CONFIG_SYS_INIT_SP_ADDR         0x80200000
 114
 115 /* On CCP board, USDHC1 is for eMMC */
 116 #define CONFIG_MMCROOT                  "/dev/mmcblk0p2"  /* eMMC */
 117
 118 #define CONFIG_SYS_SDRAM_BASE           0x80000000
 119 #define PHYS_SDRAM_1                    0x80000000
 120 #define PHYS_SDRAM_2                    0x880000000
 121 /* DDR3 board total DDR is 1 GB */
 122 #define PHYS_SDRAM_1_SIZE               0x40000000      /* 1 GB */
 123 #define PHYS_SDRAM_2_SIZE               0x00000000      /* 0 GB */
 124
 125 /* Console buffer and boot args */
 126 #define CONFIG_SYS_CBSIZE               2048
 127 #define CONFIG_SYS_MAXARGS              64
 128 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 129
 130 /* Generic Timer Definitions */
 131 #define COUNTER_FREQUENCY               8000000 /* 8MHz */
 132
 133 #define BOOTAUX_RESERVED_MEM_BASE       0x88000000
 134 #define BOOTAUX_RESERVED_MEM_SIZE       SZ_128M /* Reserve from second 128MB */
 135
 136 #endif /* __IMX8X_CAPRICORN_H */