include/configs/capricorn-common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017-2018 NXP
   4  * Copyright 2019 Siemens AG
   5  */
   6
   7 #ifndef __IMX8X_CAPRICORN_H
   8 #define __IMX8X_CAPRICORN_H
   9
  10 #include <linux/sizes.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #include "siemens-env-common.h"
  14
  15 /* SPL config */
  16 #ifdef CONFIG_SPL_BUILD
  17 #define CFG_MALLOC_F_ADDR               0x00120000
  18
  19 #endif /* CONFIG_SPL_BUILD */
  20
  21 /* ENET1 connects to base board and MUX with ESAI */
  22 #define CFG_FEC_ENET_DEV                1
  23 #define CFG_FEC_MXC_PHYADDR             0x0
  24
  25 /* EEPROM */
  26 #define  EEPROM_I2C_BUS         0 /* I2C0 */
  27 #define  EEPROM_I2C_ADDR        0x50
  28 /* PCA9552 */
  29 #define  PCA9552_1_I2C_BUS      1 /* I2C1 */
  30 #define  PCA9552_1_I2C_ADDR     0x60
  31
  32 /* AHAB */
  33 #ifdef CONFIG_AHAB_BOOT
  34 #define AHAB_ENV "sec_boot=yes\0"
  35 #else
  36 #define AHAB_ENV "sec_boot=no\0"
  37 #endif
  38
  39 #define MFG_ENV_SETTINGS_DEFAULT \
  40         "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  41                 "rdinit=/linuxrc " \
  42                 "clk_ignore_unused "\
  43                 "\0" \
  44         "kboot=booti\0"\
  45         "bootcmd_mfg=run mfgtool_args;" \
  46         "if iminfo ${initrd_addr}; then " \
  47         "if test ${tee} = yes; then " \
  48                 "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
  49         "else " \
  50                 "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
  51         "fi; " \
  52         "else " \
  53             "echo \"Run fastboot ...\"; fastboot 0; "  \
  54         "fi;\0"
  55
  56 /* Boot M4 */
  57 #define M4_BOOT_ENV \
  58         "m4_0_image=m4_0.bin\0" \
  59         "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
  60                         "${loadaddr} ${m4_0_image}\0" \
  61         "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  62
  63 #define CFG_MFG_ENV_SETTINGS \
  64         MFG_ENV_SETTINGS_DEFAULT \
  65         "initrd_addr=0x83100000\0" \
  66         "initrd_high=0xffffffffffffffff\0" \
  67         "emmc_dev=0\0"
  68
  69 /* Initial environment variables */
  70 #define CFG_EXTRA_ENV_SETTINGS \
  71         CFG_MFG_ENV_SETTINGS \
  72         M4_BOOT_ENV \
  73         AHAB_ENV \
  74         ENV_COMMON \
  75         "script=boot.scr\0" \
  76         "image=Image\0" \
  77         "panel=NULL\0" \
  78         "console=ttyLP2\0" \
  79         "fdt_addr=0x83000000\0" \
  80         "fdt_high=0xffffffffffffffff\0" \
  81         "cntr_addr=0x88000000\0" \
  82         "cntr_file=os_cntr_signed.bin\0" \
  83         "initrd_addr=0x83800000\0" \
  84         "initrd_high=0xffffffffffffffff\0" \
  85         "netdev=eth0\0" \
  86         "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
  87         "hostname=capricorn\0" \
  88         ENV_EMMC \
  89         ENV_NET
  90
  91 /* Default location for tftp and bootm */
  92
  93 /* On CCP board, USDHC1 is for eMMC */
  94
  95 #define CFG_SYS_SDRAM_BASE              0x80000000
  96 #define PHYS_SDRAM_1                    0x80000000
  97 #define PHYS_SDRAM_2                    0x880000000
  98 /* DDR3 board total DDR is 1 GB */
  99 #define PHYS_SDRAM_1_SIZE               0x40000000      /* 1 GB */
 100 #define PHYS_SDRAM_2_SIZE               0x00000000      /* 0 GB */
 101
 102 #define BOOTAUX_RESERVED_MEM_BASE       0x88000000
 103 #define BOOTAUX_RESERVED_MEM_SIZE       SZ_128M /* Reserve from second 128MB */
 104
 105 #endif /* __IMX8X_CAPRICORN_H */