1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
4 * Copyright 2019 Siemens AG
7 #ifndef __IMX8X_CAPRICORN_H
8 #define __IMX8X_CAPRICORN_H
10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h>
13 #include "siemens-env-common.h"
16 #ifdef CONFIG_SPL_BUILD
18 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
20 #define CONFIG_SPL_STACK 0x013E000
21 #define CONFIG_SPL_BSS_START_ADDR 0x00128000
22 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
23 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
24 #define CONFIG_MALLOC_F_ADDR 0x00120000
26 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
27 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
29 #endif /* CONFIG_SPL_BUILD */
31 #define CONFIG_FACTORYSET
33 /* ENET1 connects to base board and MUX with ESAI */
34 #define CONFIG_FEC_ENET_DEV 1
35 #define CONFIG_FEC_MXC_PHYADDR 0x0
37 /* I2C Configuration */
38 #ifndef CONFIG_SPL_BUILD
40 #define EEPROM_I2C_BUS 0 /* I2C0 */
41 #define EEPROM_I2C_ADDR 0x50
43 #define PCA9552_1_I2C_BUS 1 /* I2C1 */
44 #define PCA9552_1_I2C_ADDR 0x60
45 #endif /* !CONFIG_SPL_BUILD */
48 #ifdef CONFIG_AHAB_BOOT
49 #define AHAB_ENV "sec_boot=yes\0"
51 #define AHAB_ENV "sec_boot=no\0"
54 #define MFG_ENV_SETTINGS_DEFAULT \
55 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
60 "bootcmd_mfg=run mfgtool_args;" \
61 "if iminfo ${initrd_addr}; then " \
62 "if test ${tee} = yes; then " \
63 "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
65 "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
68 "echo \"Run fastboot ...\"; fastboot 0; " \
73 "m4_0_image=m4_0.bin\0" \
74 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
75 "${loadaddr} ${m4_0_image}\0" \
76 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
78 #define CONFIG_MFG_ENV_SETTINGS \
79 MFG_ENV_SETTINGS_DEFAULT \
80 "initrd_addr=0x83100000\0" \
81 "initrd_high=0xffffffffffffffff\0" \
84 /* Initial environment variables */
85 #define CONFIG_EXTRA_ENV_SETTINGS \
86 CONFIG_MFG_ENV_SETTINGS \
94 "fdt_addr=0x83000000\0" \
95 "fdt_high=0xffffffffffffffff\0" \
96 "cntr_addr=0x88000000\0" \
97 "cntr_file=os_cntr_signed.bin\0" \
98 "initrd_addr=0x83800000\0" \
99 "initrd_high=0xffffffffffffffff\0" \
101 "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
102 "hostname=capricorn\0" \
106 /* Default location for tftp and bootm */
107 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
109 /* On CCP board, USDHC1 is for eMMC */
111 #define CONFIG_SYS_SDRAM_BASE 0x80000000
112 #define PHYS_SDRAM_1 0x80000000
113 #define PHYS_SDRAM_2 0x880000000
114 /* DDR3 board total DDR is 1 GB */
115 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
116 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
118 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
119 #define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
121 #endif /* __IMX8X_CAPRICORN_H */