1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017-2018 NXP
4 * Copyright 2019 Siemens AG
7 #ifndef __IMX8X_CAPRICORN_H
8 #define __IMX8X_CAPRICORN_H
10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h>
13 #include "siemens-env-common.h"
16 #ifdef CONFIG_SPL_BUILD
18 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
19 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
21 #define CONFIG_SPL_STACK 0x013E000
22 #define CONFIG_SPL_BSS_START_ADDR 0x00128000
23 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
24 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
25 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
26 #define CONFIG_MALLOC_F_ADDR 0x00120000
28 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
29 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
31 #endif /* CONFIG_SPL_BUILD */
33 #define CONFIG_FACTORYSET
35 /* ENET1 connects to base board and MUX with ESAI */
36 #define CONFIG_FEC_ENET_DEV 1
37 #define CONFIG_FEC_MXC_PHYADDR 0x0
39 /* I2C Configuration */
40 #ifndef CONFIG_SPL_BUILD
42 #define EEPROM_I2C_BUS 0 /* I2C0 */
43 #define EEPROM_I2C_ADDR 0x50
45 #define PCA9552_1_I2C_BUS 1 /* I2C1 */
46 #define PCA9552_1_I2C_ADDR 0x60
47 #endif /* !CONFIG_SPL_BUILD */
50 #ifdef CONFIG_AHAB_BOOT
51 #define AHAB_ENV "sec_boot=yes\0"
53 #define AHAB_ENV "sec_boot=no\0"
56 #define MFG_ENV_SETTINGS_DEFAULT \
57 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
62 "bootcmd_mfg=run mfgtool_args;" \
63 "if iminfo ${initrd_addr}; then " \
64 "if test ${tee} = yes; then " \
65 "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
67 "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
70 "echo \"Run fastboot ...\"; fastboot 0; " \
75 "m4_0_image=m4_0.bin\0" \
76 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
77 "${loadaddr} ${m4_0_image}\0" \
78 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
80 #define CONFIG_MFG_ENV_SETTINGS \
81 MFG_ENV_SETTINGS_DEFAULT \
82 "initrd_addr=0x83100000\0" \
83 "initrd_high=0xffffffffffffffff\0" \
86 /* Initial environment variables */
87 #define CONFIG_EXTRA_ENV_SETTINGS \
88 CONFIG_MFG_ENV_SETTINGS \
96 "fdt_addr=0x83000000\0" \
97 "fdt_high=0xffffffffffffffff\0" \
98 "cntr_addr=0x88000000\0" \
99 "cntr_file=os_cntr_signed.bin\0" \
100 "initrd_addr=0x83800000\0" \
101 "initrd_high=0xffffffffffffffff\0" \
103 "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
104 "hostname=capricorn\0" \
108 /* Default location for tftp and bootm */
109 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
111 /* On CCP board, USDHC1 is for eMMC */
113 #define CONFIG_SYS_SDRAM_BASE 0x80000000
114 #define PHYS_SDRAM_1 0x80000000
115 #define PHYS_SDRAM_2 0x880000000
116 /* DDR3 board total DDR is 1 GB */
117 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
118 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
120 /* Console buffer and boot args */
121 #define CONFIG_SYS_CBSIZE 2048
122 #define CONFIG_SYS_MAXARGS 64
123 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
125 /* Generic Timer Definitions */
126 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
128 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
129 #define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
131 #endif /* __IMX8X_CAPRICORN_H */