3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 /************************************************************************
9 * canyonlands.h - configuration for Canyonlands (460EX)
10 ***********************************************************************/
14 #include <linux/kconfig.h>
16 /*-----------------------------------------------------------------------
17 * High Level Configuration Options
18 *----------------------------------------------------------------------*/
20 * This config file is used for Canyonlands (460EX) Glacier (460GT)
21 * and Arches dual (460GT)
23 #ifdef CONFIG_CANYONLANDS
24 #define CONFIG_460EX /* Specific PPC460EX */
25 #define CONFIG_HOSTNAME canyonlands
27 #define CONFIG_460GT /* Specific PPC460GT */
29 #define CONFIG_HOSTNAME glacier
31 #define CONFIG_HOSTNAME arches
32 #define CONFIG_USE_NETDEV eth1
33 #define CONFIG_BD_NUM_CPUS 2
39 #ifndef CONFIG_SYS_TEXT_BASE
40 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
44 * Include common defines/options for all AMCC eval boards
46 #include "amcc-common.h"
48 #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
50 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
51 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
52 #define CONFIG_MISC_INIT_R /* Call misc_init_r */
53 #define CONFIG_BOARD_TYPES /* support board types */
55 /*-----------------------------------------------------------------------
56 * Base addresses -- Note these are effective addresses where the
57 * actual resources get mapped (not physical addresses)
58 *----------------------------------------------------------------------*/
59 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
60 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
61 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
63 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
64 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
65 #define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
67 #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
68 #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
69 #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
70 #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
73 * BCSR bits as defined in the Canyonlands board user manual.
75 #define BCSR_USBCTRL_OTG_RST 0x32
76 #define BCSR_USBCTRL_HOST_RST 0x01
77 #define BCSR_SELECT_PCIE 0x10
79 #define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
81 /* base address of inbound PCIe window */
82 #define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
85 #if !defined(CONFIG_ARCHES)
86 #define CONFIG_SYS_BCSR_BASE 0xE1000000
87 #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped to this addr */
88 #define CONFIG_SYS_FLASH_SIZE (64 << 20)
90 #define CONFIG_SYS_FPGA_BASE 0xE1000000
91 #define CONFIG_SYS_CPLD_ADDR (CONFIG_SYS_FPGA_BASE + 0x00080000)
92 #define CONFIG_SYS_CPLD_DATA (CONFIG_SYS_FPGA_BASE + 0x00080002)
93 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* later mapped to this addr */
94 #define CONFIG_SYS_FLASH_SIZE (32 << 20)
97 #define CONFIG_SYS_NAND_ADDR 0xE0000000
98 #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
99 #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
100 #define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
101 #define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
102 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
104 #define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
105 #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
106 #define CONFIG_SYS_SRAM_SIZE (256 << 10)
107 #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
109 #define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals */
111 /*-----------------------------------------------------------------------
112 * Initial RAM & stack pointer (placed in OCM)
113 *----------------------------------------------------------------------*/
114 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
115 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
116 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
117 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
119 /*-----------------------------------------------------------------------
121 *----------------------------------------------------------------------*/
122 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
124 /*-----------------------------------------------------------------------
126 *----------------------------------------------------------------------*/
128 * Define here the location of the environment variables (FLASH).
130 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
131 #define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
132 #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
134 /*-----------------------------------------------------------------------
136 *----------------------------------------------------------------------*/
137 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
138 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
139 #define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */
141 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
142 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
143 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
145 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
146 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
149 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
151 #ifdef CONFIG_ENV_IS_IN_FLASH
152 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
153 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
154 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
156 /* Address and size of Redundant Environment Sector */
157 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
158 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
159 #endif /* CONFIG_ENV_IS_IN_FLASH */
161 /*-----------------------------------------------------------------------
163 *----------------------------------------------------------------------*/
164 #define CONFIG_SYS_MAX_NAND_DEVICE 1
165 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
166 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
168 /*------------------------------------------------------------------------------
170 *----------------------------------------------------------------------------*/
171 #if !defined(CONFIG_ARCHES)
173 * NAND booting U-Boot version uses a fixed initialization, since the whole
174 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
177 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
178 #define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
179 #define CONFIG_DDR_ECC /* with ECC support */
180 #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
182 #else /* defined(CONFIG_ARCHES) */
184 #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
186 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
187 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
188 #undef CONFIG_PPC4xx_DDR_METHOD_A
190 /* DDR1/2 SDRAM Device Control Register Data Values */
192 #define CONFIG_SYS_SDRAM_R0BAS 0x0000f000
193 #define CONFIG_SYS_SDRAM_R1BAS 0x00000000
194 #define CONFIG_SYS_SDRAM_R2BAS 0x00000000
195 #define CONFIG_SYS_SDRAM_R3BAS 0x00000000
196 #define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
197 #define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
198 #define CONFIG_SYS_SDRAM_CONF1LL 0x00001080
199 #define CONFIG_SYS_SDRAM_CONF1HB 0x00001080
200 #define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
202 /* SDRAM Controller */
203 #define CONFIG_SYS_SDRAM0_MB0CF 0x00000701
204 #define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
205 #define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
206 #define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
207 #define CONFIG_SYS_SDRAM0_MCOPT1 0x05322000
208 #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
209 #define CONFIG_SYS_SDRAM0_MODT0 0x01000000
210 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
211 #define CONFIG_SYS_SDRAM0_MODT2 0x00000000
212 #define CONFIG_SYS_SDRAM0_MODT3 0x00000000
213 #define CONFIG_SYS_SDRAM0_CODT 0x00800021
214 #define CONFIG_SYS_SDRAM0_RTR 0x06180000
215 #define CONFIG_SYS_SDRAM0_INITPLR0 0xb5380000
216 #define CONFIG_SYS_SDRAM0_INITPLR1 0x82100400
217 #define CONFIG_SYS_SDRAM0_INITPLR2 0x80820000
218 #define CONFIG_SYS_SDRAM0_INITPLR3 0x80830000
219 #define CONFIG_SYS_SDRAM0_INITPLR4 0x80810040
220 #define CONFIG_SYS_SDRAM0_INITPLR5 0x80800532
221 #define CONFIG_SYS_SDRAM0_INITPLR6 0x82100400
222 #define CONFIG_SYS_SDRAM0_INITPLR7 0x8a080000
223 #define CONFIG_SYS_SDRAM0_INITPLR8 0x8a080000
224 #define CONFIG_SYS_SDRAM0_INITPLR9 0x8a080000
225 #define CONFIG_SYS_SDRAM0_INITPLR10 0x8a080000
226 #define CONFIG_SYS_SDRAM0_INITPLR11 0x80000432
227 #define CONFIG_SYS_SDRAM0_INITPLR12 0x808103c0
228 #define CONFIG_SYS_SDRAM0_INITPLR13 0x80810040
229 #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
230 #define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
231 #define CONFIG_SYS_SDRAM0_RQDC 0x80000038
232 #define CONFIG_SYS_SDRAM0_RFDC 0x00000257
233 #define CONFIG_SYS_SDRAM0_RDCC 0x40000000
234 #define CONFIG_SYS_SDRAM0_DLCR 0x03000091
235 #define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
236 #define CONFIG_SYS_SDRAM0_WRDTR 0x82000823
237 #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
238 #define CONFIG_SYS_SDRAM0_SDTR2 0x42204243
239 #define CONFIG_SYS_SDRAM0_SDTR3 0x090c0d1a
240 #define CONFIG_SYS_SDRAM0_MMODE 0x00000432
241 #define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
242 #endif /* !defined(CONFIG_ARCHES) */
244 #define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
246 /*-----------------------------------------------------------------------
248 *----------------------------------------------------------------------*/
249 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
251 #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
252 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
256 /* I2C bootstrap EEPROM */
257 #if defined(CONFIG_ARCHES)
258 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
260 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
262 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
263 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16
265 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
266 #define CONFIG_DTT_LM75 /* ON Semi's LM75 */
267 #define CONFIG_DTT_AD7414 /* use AD7414 */
268 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
269 #define CONFIG_SYS_DTT_MAX_TEMP 70
270 #define CONFIG_SYS_DTT_LOW_TEMP -30
271 #define CONFIG_SYS_DTT_HYSTERESIS 3
273 #if defined(CONFIG_ARCHES)
274 #define CONFIG_SYS_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */
277 #if !defined(CONFIG_ARCHES)
278 /* RTC configuration */
279 #define CONFIG_RTC_M41T62
280 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
283 /*-----------------------------------------------------------------------
285 *----------------------------------------------------------------------*/
286 #define CONFIG_IBM_EMAC4_V4
288 #define CONFIG_HAS_ETH0
289 #define CONFIG_HAS_ETH1
291 #if !defined(CONFIG_ARCHES)
292 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
293 #define CONFIG_PHY1_ADDR 1
294 /* Only Glacier (460GT) has 4 EMAC interfaces */
296 #define CONFIG_PHY2_ADDR 2
297 #define CONFIG_PHY3_ADDR 3
298 #define CONFIG_HAS_ETH2
299 #define CONFIG_HAS_ETH3
302 #else /* defined(CONFIG_ARCHES) */
304 #define CONFIG_FIXED_PHY 0xFFFFFFFF
305 #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
306 #define CONFIG_PHY1_ADDR 0
307 #define CONFIG_PHY2_ADDR 1
308 #define CONFIG_HAS_ETH2
310 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
311 {devnum, speed, duplex}
312 #define CONFIG_SYS_FIXED_PHY_PORTS \
313 CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
315 #define CONFIG_M88E1112_PHY
318 * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
319 * used by CONFIG_PHYx_ADDR
321 #define CONFIG_GPCS_PHY_ADDR 0xA
322 #define CONFIG_GPCS_PHY1_ADDR 0xB
323 #define CONFIG_GPCS_PHY2_ADDR 0xC
324 #endif /* !defined(CONFIG_ARCHES) */
326 #define CONFIG_PHY_RESET /* reset phy upon startup */
327 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
328 #define CONFIG_PHY_DYNAMIC_ANEG
330 /*-----------------------------------------------------------------------
332 *----------------------------------------------------------------------*/
333 /* Only Canyonlands (460EX) has USB */
335 #define CONFIG_USB_OHCI_NEW
336 #define CONFIG_USB_STORAGE
337 #undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
338 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
339 #define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
340 #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
341 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
342 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
343 #define CONFIG_SYS_USB_OHCI_BOARD_INIT
347 * Default environment variables
349 #if !defined(CONFIG_ARCHES)
350 #define CONFIG_EXTRA_ENV_SETTINGS \
351 CONFIG_AMCC_DEF_ENV \
352 CONFIG_AMCC_DEF_ENV_POWERPC \
353 CONFIG_AMCC_DEF_ENV_NOR_UPD \
354 "kernel_addr=fc000000\0" \
355 "fdt_addr=fc1e0000\0" \
356 "ramdisk_addr=fc200000\0" \
357 "pciconfighost=1\0" \
358 "pcie_mode=RP:RP\0" \
360 #else /* defined(CONFIG_ARCHES) */
361 #define CONFIG_EXTRA_ENV_SETTINGS \
362 CONFIG_AMCC_DEF_ENV \
363 CONFIG_AMCC_DEF_ENV_POWERPC \
364 CONFIG_AMCC_DEF_ENV_NOR_UPD \
365 "kernel_addr=fe000000\0" \
366 "fdt_addr=fe1e0000\0" \
367 "ramdisk_addr=fe200000\0" \
368 "pciconfighost=1\0" \
369 "pcie_mode=RP:RP\0" \
370 "ethprime=ppc_4xx_eth1\0" \
372 #endif /* !defined(CONFIG_ARCHES) */
375 * Commands additional to the ones defined in amcc-common.h
377 #define CONFIG_CMD_CHIP_CONFIG
378 #if defined(CONFIG_ARCHES)
379 #define CONFIG_CMD_DTT
380 #define CONFIG_CMD_PCI
381 #define CONFIG_CMD_SDRAM
382 #elif defined(CONFIG_CANYONLANDS)
383 #define CONFIG_CMD_DATE
384 #define CONFIG_CMD_DTT
385 #define CONFIG_CMD_EXT2
386 #define CONFIG_CMD_FAT
387 #define CONFIG_CMD_NAND
388 #define CONFIG_CMD_PCI
389 #define CONFIG_CMD_SATA
390 #define CONFIG_CMD_SDRAM
391 #define CONFIG_CMD_SNTP
392 #define CONFIG_CMD_USB
393 #elif defined(CONFIG_GLACIER)
394 #define CONFIG_CMD_DATE
395 #define CONFIG_CMD_DTT
396 #define CONFIG_CMD_NAND
397 #define CONFIG_CMD_PCI
398 #define CONFIG_CMD_SDRAM
399 #define CONFIG_CMD_SNTP
401 #error "board type not defined"
405 #define CONFIG_MAC_PARTITION
406 #define CONFIG_DOS_PARTITION
407 #define CONFIG_ISO_PARTITION
409 /*-----------------------------------------------------------------------
411 *----------------------------------------------------------------------*/
413 #define CONFIG_PCI /* include pci support */
414 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
415 #define CONFIG_PCI_PNP /* do pci plug-and-play */
416 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
417 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
419 /* Board-specific PCI */
420 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
421 #undef CONFIG_SYS_PCI_MASTER_INIT
423 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
424 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
427 #if defined(CONFIG_ARCHES)
428 /*-----------------------------------------------------------------------
429 * RapidIO I/O and Registers
430 *----------------------------------------------------------------------*/
431 #define CONFIG_RAPIDIO
432 #define CONFIG_SYS_460GT_SRIO_ERRATA_1
434 #define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */
435 #define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */
436 #define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */
437 #define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */
438 #define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
440 #define CONFIG_SYS_SRGPL0_REG_BAR 0xAA000000 /* 16MB */
441 #define CONFIG_SYS_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */
442 #define CONFIG_SYS_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */
443 #define CONFIG_SYS_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
445 #define CONFIG_SYS_I2ODMA_BASE 0xCF000000
446 #define CONFIG_SYS_I2ODMA_PHYS_ADDR 0x0000000400100000ull
448 #define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
449 #undef CONFIG_PPC4XX_RAPIDIO_DEBUG
450 #undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
451 #define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
452 #undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
453 #endif /* CONFIG_ARCHES */
454 #endif /* CONFIG_460GT */
459 #ifdef CONFIG_CMD_SATA
460 #define CONFIG_SATA_DWC
461 #define CONFIG_LIBATA
462 #define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */
463 #define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */
464 #define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */
465 /* Convert sectorsize to wordsize */
466 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
469 /*-----------------------------------------------------------------------
470 * External Bus Controller (EBC) Setup
471 *----------------------------------------------------------------------*/
474 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
475 * boot EBC mapping only supports a maximum of 16MBytes
476 * (4.ff00.0000 - 4.ffff.ffff).
477 * To solve this problem, the FLASH has to get remapped to another
478 * EBC address which accepts bigger regions:
480 * 0xfc00.0000 -> 4.cc00.0000
482 * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
485 * 0xfe00.0000 -> 4.ce00.0000
488 /* Memory Bank 0 (NOR-FLASH) initialization */
489 #define CONFIG_SYS_EBC_PB0AP 0x10055e00
490 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
492 #if !defined(CONFIG_ARCHES)
493 /* Memory Bank 3 (NAND-FLASH) initialization */
494 #define CONFIG_SYS_EBC_PB3AP 0x018003c0
495 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
498 #if !defined(CONFIG_ARCHES)
499 /* Memory Bank 2 (CPLD) initialization */
500 #define CONFIG_SYS_EBC_PB2AP 0x00804240
501 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
503 #else /* defined(CONFIG_ARCHES) */
505 /* Memory Bank 1 (FPGA) initialization */
506 #define CONFIG_SYS_EBC_PB1AP 0x7f8ffe80
507 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
508 #endif /* !defined(CONFIG_ARCHES) */
510 #define CONFIG_SYS_EBC_CFG 0xbfc00000
513 * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
514 * pin multiplexing correctly
516 #if defined(CONFIG_ARCHES)
517 #define GPIO43_USE GPIO_SEL /* On Arches this pin is used as GPIO */
519 #define GPIO43_USE GPIO_ALT1 /* On Glacier this pin is used as ALT1 -> PerCS3 */
523 * PPC4xx GPIO Configuration
526 /* 460EX: Use USB configuration */
527 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
530 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
531 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
532 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
533 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
534 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
535 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
536 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
537 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
538 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
539 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
540 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
541 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
542 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
543 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
544 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
545 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
546 {GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
547 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
548 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
549 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
550 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
551 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
552 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
553 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
554 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
555 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
556 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
557 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
558 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
559 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
560 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
561 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
565 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
566 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
567 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
568 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
569 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
570 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
571 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
572 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
573 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
574 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
575 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
576 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
577 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
578 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
579 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
580 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
581 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
582 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
583 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
584 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
585 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
586 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
587 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
588 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
589 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
590 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
591 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
592 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
593 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
594 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
595 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
596 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
600 /* 460GT: Use EMAC2+3 configuration */
601 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
604 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
605 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
606 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
607 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
608 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
609 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
610 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
611 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
612 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
613 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
614 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
615 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
616 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
617 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
618 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
619 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
620 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
621 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
622 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
623 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
624 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
625 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
626 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
627 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
628 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
629 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
630 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
631 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
632 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
633 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
634 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
635 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
639 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
640 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
641 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
642 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
643 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
644 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
645 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
646 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
647 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
648 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
649 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
650 {GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
651 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
652 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
653 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
654 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
655 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
656 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
657 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
658 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
659 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
660 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
661 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
662 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
663 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
664 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
665 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
666 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
667 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
668 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
669 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
670 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
675 #endif /* __CONFIG_H */