2 * Copyright (C) 2009 Texas Instruments Incorporated
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
13 #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
14 #define CONFIG_SYS_CONSOLE_INFO_QUIET
16 /* SoC Configuration */
17 #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
18 #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
19 #define CONFIG_SOC_DM365
21 #define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
23 #define CONFIG_HOSTNAME cam_enc_4xx
25 #define CONFIG_BOARD_LATE_INIT
26 #define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
29 #define CONFIG_NR_DRAM_BANKS 1
30 #define PHYS_SDRAM_1 0x80000000
31 #define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
32 #define DDR_4BANKS /* 4-bank DDR2 (256MB) */
33 #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
34 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
36 /* Serial Driver info: UART0 for console */
37 #define CONFIG_SYS_NS16550
38 #define CONFIG_SYS_NS16550_SERIAL
39 #define CONFIG_SYS_NS16550_REG_SIZE -4
40 #define CONFIG_SYS_NS16550_COM1 0x01c20000
41 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
42 #define CONFIG_CONS_INDEX 1
43 #define CONFIG_BAUDRATE 115200
45 /* Network Configuration */
46 #define CONFIG_DRIVER_TI_EMAC
47 #define CONFIG_EMAC_MDIO_PHY_NUM 0
48 #define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
50 #define CONFIG_BOOTP_DNS
51 #define CONFIG_BOOTP_DNS2
52 #define CONFIG_BOOTP_SEND_HOSTNAME
53 #define CONFIG_NET_RETRY_COUNT 10
54 #define CONFIG_CMD_MII
55 #define CONFIG_SYS_DCACHE_OFF
56 #define CONFIG_RESET_PHY_R
59 #define CONFIG_SYS_I2C
60 #define CONFIG_SYS_I2C_DAVINCI
61 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
62 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
64 /* NAND: socketed, two chipselects, normally 2 GBytes */
65 #define CONFIG_NAND_DAVINCI
66 #define CONFIG_SYS_NAND_CS 2
67 #define CONFIG_SYS_NAND_USE_FLASH_BBT
68 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
69 #define CONFIG_SYS_NAND_PAGE_2K
71 #define CONFIG_SYS_NAND_LARGEPAGE
72 #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
73 /* socket has two chipselects, nCE0 gated by address BIT(14) */
74 #define CONFIG_SYS_MAX_NAND_DEVICE 1
78 #define CONFIG_SPI_FLASH_STMICRO
79 #define CONFIG_DAVINCI_SPI
80 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
81 #define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
82 #define CONFIG_SF_DEFAULT_SPEED 3000000
83 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
88 #define CONFIG_GENERIC_MMC
89 #define CONFIG_DAVINCI_MMC
90 #define CONFIG_MMC_MBLOCK
92 /* U-Boot command configuration */
93 #define CONFIG_CMD_ASKENV
94 #define CONFIG_CMD_CACHE
95 #define CONFIG_CMD_DHCP
96 #define CONFIG_CMD_I2C
97 #define CONFIG_CMD_PING
98 #define CONFIG_CMD_SAVES
100 #ifdef CONFIG_CMD_BDI
101 #define CONFIG_CLOCKS
105 #define CONFIG_DOS_PARTITION
106 #define CONFIG_CMD_EXT2
107 #define CONFIG_CMD_FAT
108 #define CONFIG_CMD_MMC
111 #ifdef CONFIG_NAND_DAVINCI
112 #define CONFIG_CMD_MTDPARTS
113 #define CONFIG_MTD_PARTITIONS
114 #define CONFIG_MTD_DEVICE
115 #define CONFIG_CMD_NAND
116 #define CONFIG_CMD_UBI
117 #define CONFIG_CMD_UBIFS
118 #define CONFIG_RBTREE
122 #define CONFIG_CRC32_VERIFY
123 #define CONFIG_MX_CYCLIC
125 /* U-Boot general configuration */
126 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
127 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
128 #define CONFIG_SYS_PBSIZE /* Print buffer size */ \
129 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
130 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
131 #define CONFIG_SYS_HUSH_PARSER
132 #define CONFIG_SYS_LONGHELP
135 #define CONFIG_MENU_SHOW
137 #define CONFIG_BOARD_IMG_ADDR_R 0x80000000
139 #ifdef CONFIG_NAND_DAVINCI
140 #define CONFIG_ENV_SIZE (16 << 10)
141 #define CONFIG_ENV_IS_IN_NAND
142 #define CONFIG_ENV_OFFSET 0x180000
143 #define CONFIG_ENV_RANGE 0x040000
144 #define CONFIG_ENV_OFFSET_REDUND 0x1c0000
145 #undef CONFIG_ENV_IS_IN_FLASH
148 #if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
149 #define CONFIG_CMD_ENV
150 #define CONFIG_SYS_MMC_ENV_DEV 0
151 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
152 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
153 #define CONFIG_ENV_IS_IN_MMC
154 #undef CONFIG_ENV_IS_IN_FLASH
157 #define CONFIG_BOOTDELAY 3
159 * 24MHz InputClock / 15 prediv -> 1.6 MHz timer running
162 #define CONFIG_AIT_TIMER_TIMEOUT 0x186a00
164 #define CONFIG_CMDLINE_EDITING
165 #define CONFIG_VERSION_VARIABLE
166 #define CONFIG_TIMESTAMP
168 /* U-Boot memory configuration */
169 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
170 #define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
171 #define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
173 /* Linux interfacing */
174 #define CONFIG_CMDLINE_TAG
175 #define CONFIG_SETUP_MEMORY_TAGS
176 #define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
177 #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
179 #define MTDIDS_DEFAULT "nand0=davinci_nand.0"
180 #define MTDPARTS_DEFAULT \
189 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
190 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
192 /* Defines for SPL */
193 #define CONFIG_SPL_FRAMEWORK
194 #define CONFIG_SPL_BOARD_INIT
195 #define CONFIG_SPL_LIBGENERIC_SUPPORT
196 #define CONFIG_SPL_NAND_SUPPORT
197 #define CONFIG_SPL_NAND_BASE
198 #define CONFIG_SPL_NAND_DRIVERS
199 #define CONFIG_SPL_NAND_ECC
200 #define CONFIG_SPL_NAND_SIMPLE
201 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
202 #define CONFIG_SPL_SERIAL_SUPPORT
203 #define CONFIG_SPL_POST_MEM_SUPPORT
204 #define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
205 #define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
207 #define CONFIG_SPL_TEXT_BASE 0x00000020 /*CONFIG_SYS_SRAM_START*/
208 /* Provide at least 16MB spacing between us and the Linux Kernel image */
209 #define CONFIG_SPL_PAD_TO 12320
210 #define CONFIG_SPL_MAX_FOOTPRINT 12288
212 #ifndef CONFIG_SPL_BUILD
213 #define CONFIG_SYS_TEXT_BASE 0x81080000
216 #define CONFIG_SYS_NAND_BASE 0x02000000
217 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
218 CONFIG_SYS_NAND_PAGE_SIZE)
220 #define CONFIG_SYS_NAND_ECCPOS { \
221 24, 25, 26, 27, 28, \
222 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
223 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
224 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
226 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
227 #define CONFIG_SYS_NAND_ECCSIZE 0x200
228 #define CONFIG_SYS_NAND_ECCBYTES 10
229 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
230 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
231 #define CONFIG_SYS_NAND_OOBSIZE 64
232 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
235 * RBL searches from Block n (n = 1..24)
236 * so we can define, how many UBL Headers
237 * we can write before the real spl code
239 #define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
241 #define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
242 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
245 * Post tests for memory testing
247 #define CONFIG_POST CONFIG_SYS_POST_MEMORY
248 #define _POST_WORD_ADDR 0x0
250 #define CONFIG_DISPLAY_BOARDINFO
252 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
254 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
255 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
256 #define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE 0x100000
259 #define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
261 #define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
262 #define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
263 #define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
264 #define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
265 #define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
266 #define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
267 #define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
268 /* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
269 #define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
271 * POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
274 #define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
275 /* POST DIV 680/2 = 340Mhz -> VPSS */
276 #define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
277 /* POST DIV 680/9 = 75.6 Mhz -> VENC */
278 #define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
280 * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
283 #define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
284 /* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
285 #define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
286 /* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
287 #define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
289 #define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
290 /* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
291 #define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
292 #define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
293 /* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
294 #define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
295 /* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
296 #define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
299 * READ LATENCY 7 (CL + 2)
301 * CONFIG_EXT_STRBEN = 1
303 #define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
304 | DV_DDR_PHY_EXT_STRBEN \
305 | DV_DDR_PHY_PWRDNEN \
306 | (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
309 * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
310 * T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
311 * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
312 * T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
313 * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
314 * T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
315 * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
316 * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
318 #define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
319 | (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
320 | (4 << DV_DDR_SDTMR1_RP_SHIFT) \
321 | (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
322 | (5 << DV_DDR_SDTMR1_WR_SHIFT) \
323 | (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
324 | (19 << DV_DDR_SDTMR1_RC_SHIFT) \
325 | (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
326 | (2 << DV_DDR_SDTMR1_WTR_SHIFT))
329 * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
330 * T_XP = tCKE - 1 = 3 - 2
331 * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
332 * T_XSRD = txsrd - 1 = 200 - 1
333 * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
334 * T_CKE = tcke - 1 = 3 - 1
336 #define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
337 | (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
338 | (2 << DV_DDR_SDTMR2_XP_SHIFT) \
339 | (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
340 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
341 | (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
342 | (2 << DV_DDR_SDTMR2_CKE_SHIFT))
344 /* PR_OLD_COUNT = 0xfe */
345 #define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
346 /* refresh rate = 0x768 */
347 #define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
349 #define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
350 | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
351 | (3 << DV_DDR_SDCR_IBANK_SHIFT) \
352 | (5 << DV_DDR_SDCR_CL_SHIFT) \
353 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
354 | (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
355 | (1 << DV_DDR_SDCR_DDREN_SHIFT) \
356 | (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
357 | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
358 | (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
359 | (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
361 #define CONFIG_SYS_DM36x_AWCCR 0xff
362 #define CONFIG_SYS_DM36x_AB1CR 0x40400204
363 #define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
365 /* All Video Inputs */
366 #define CONFIG_SYS_DM36x_PINMUX0 0x00000000
369 * GPIO 86, 87 + 90 0x0000f030
371 #define CONFIG_SYS_DM36x_PINMUX1 0x00530002
372 #define CONFIG_SYS_DM36x_PINMUX2 0x00001815
374 * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
377 #define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
379 * MMC/SD0 instead of MS, SPI0
382 #define CONFIG_SYS_DM36x_PINMUX4 0x00002655
385 * Default environment settings
388 #define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
389 /* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
390 #define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
392 * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
393 * CONFIG_SYS_NAND_PAGE_SIZE))
395 #define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
397 #define CONFIG_EXTRA_ENV_SETTINGS \
398 "u_boot_addr_r=" __stringify(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
399 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
400 "load=tftp ${u_boot_addr_r} ${u-boot}\0" \
401 "pagesz=" __stringify(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
402 "writeheader=nandrbl rbl;nand erase 20000 ${pagesz};" \
403 "nand write ${u_boot_addr_r} 20000 ${pagesz};" \
405 "writenand_spl=nandrbl rbl;nand erase 0 3000;" \
406 "nand write " __stringify(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
407 " 0 3000;nandrbl uboot\0" \
408 "writeuboot=nandrbl uboot;" \
409 "nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
410 __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
411 ";nand write " __stringify(DVN4XX_UBOOT_ADDR_R_UBOOT) \
412 " " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
413 __stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
414 "update=run load writenand_spl writeuboot\0" \
415 "bootcmd=run net_nfs\0" \
416 "rootpath=/opt/eldk-arm/arm\0" \
417 "mtdids=" MTDIDS_DEFAULT "\0" \
418 "mtdparts=" MTDPARTS_DEFAULT "\0" \
420 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
421 "addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0" \
422 "addcon=setenv bootargs ${bootargs} console=ttyS0," \
424 "addip=setenv bootargs ${bootargs} " \
425 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
426 ":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0" \
427 "rootpath=/opt/eldk-arm/arm\0" \
428 "nfsargs=setenv bootargs root=/dev/nfs rw " \
429 "nfsroot=${serverip}:${rootpath}\0" \
430 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
431 "kernel_addr_r=80600000\0" \
432 "load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \
433 "ubi_load_kernel=ubi part ubi 2048;ubifsmount ubi:${img_volume};" \
434 "ubifsload ${kernel_addr_r} boot/uImage\0" \
435 "fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
436 "img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
437 "img_file=" __stringify(CONFIG_HOSTNAME) "/ait.itb\0" \
438 "header_addr=20000\0" \
439 "img_writeheader=nandrbl rbl;" \
440 "nand erase ${header_addr} ${pagesz};" \
441 "nand write ${img_addr_r} ${header_addr} ${pagesz};" \
443 "img_writespl=nandrbl rbl;nand erase 0 3000;" \
444 "nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \
445 "img_writeuboot=nandrbl uboot;" \
446 "nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
447 __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
448 ";nand write ${img_addr_r} " \
449 __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
450 __stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
451 "img_writedfenv=ubi part ubi 2048;" \
452 "ubi write ${img_addr_r} default ${filesize}\0" \
453 "img_volume=rootfs1\0" \
454 "img_writeramdisk=ubi part ubi 2048;" \
455 "ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \
456 "load_img=tftp ${fit_addr_r} ${img_file}\0" \
457 "net_nfs=run load_kernel; " \
458 "run nfsargs addip addcon addmtd addmisc;" \
459 "bootm ${kernel_addr_r}\0" \
460 "ubi_ubi=run ubi_load_kernel; " \
461 "run ubiargs addip addcon addmtd addmisc;" \
462 "bootm ${kernel_addr_r}\0" \
463 "ubiargs=setenv bootargs ubi.mtd=4,2048" \
464 " root=ubi0:${img_volume} rw rootfstype=ubifs\0" \
466 "dvn_app_vers=void\0" \
467 "dvn_boot_vers=void\0" \
468 "savenewvers=run savetmpparms restoreparms; saveenv;" \
469 "run restoretmpparms\0" \
470 "savetmpparms=setenv y_ipaddr ${ipaddr};" \
471 "setenv y_netmask ${netmask};" \
472 "setenv y_serverip ${serverip};" \
473 "setenv y_gatewayip ${gatewayip}\0" \
474 "saveparms=setenv x_ipaddr ${ipaddr};" \
475 "setenv x_netmask ${netmask};" \
476 "setenv x_serverip ${serverip};" \
477 "setenv x_gatewayip ${gatewayip}\0" \
478 "restoreparms=setenv ipaddr ${x_ipaddr};" \
479 "setenv netmask ${x_netmask};" \
480 "setenv serverip ${x_serverip};" \
481 "setenv gatewayip ${x_gatewayip}\0" \
482 "restoretmpparms=setenv ipaddr ${y_ipaddr};" \
483 "setenv netmask ${y_netmask};" \
484 "setenv serverip ${y_serverip};" \
485 "setenv gatewayip ${y_gatewayip}\0" \
488 /* USB Configuration */
489 #define CONFIG_USB_DAVINCI
490 #define CONFIG_USB_MUSB_HCD
491 #define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
494 #define CONFIG_CMD_USB /* include support for usb cmd */
495 #define CONFIG_USB_STORAGE /* MSC class support */
496 #define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
497 #define CONFIG_CMD_FAT /* inclue support for FAT/storage */
498 #define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
500 #undef DAVINCI_DM365EVM
501 #define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
502 #define PINMUX4_USBDRVBUS_BITSET 0x2000
504 #endif /* __CONFIG_H */