include/configs/cam_enc_4xx.h

   1 /*
   2  * Copyright (C) 2009 Texas Instruments Incorporated
   3  *
   4  * Copyright (C) 2011
   5  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 #define CONFIG_SYS_NO_FLASH             /* that is, no *NOR* flash */
  27 #define CONFIG_SYS_CONSOLE_INFO_QUIET
  28
  29 /* SoC Configuration */
  30 #define CONFIG_ARM926EJS                                /* arm926ejs CPU */
  31 #define CONFIG_SYS_TIMERBASE            0x01c21400      /* use timer 0 */
  32 #define CONFIG_SYS_HZ_CLOCK             24000000        /* timer0 freq */
  33 #define CONFIG_SYS_HZ                   1000
  34 #define CONFIG_SOC_DM365
  35
  36 #define CONFIG_MACH_TYPE        MACH_TYPE_DAVINCI_DM365_EVM
  37
  38 #define CONFIG_HOSTNAME                 cam_enc_4xx
  39
  40 #define BOARD_LATE_INIT
  41 #define CONFIG_CAM_ENC_LED_MASK         0x0fc00000
  42
  43 /* Memory Info */
  44 #define CONFIG_NR_DRAM_BANKS            1
  45 #define PHYS_SDRAM_1                    0x80000000
  46 #define PHYS_SDRAM_1_SIZE               (256 << 20)     /* 256 MiB */
  47 #define DDR_4BANKS                              /* 4-bank DDR2 (256MB) */
  48 #define CONFIG_MAX_RAM_BANK_SIZE        (256 << 20)     /* 256 MB */
  49 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  50
  51 /* Serial Driver info: UART0 for console  */
  52 #define CONFIG_SYS_NS16550
  53 #define CONFIG_SYS_NS16550_SERIAL
  54 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  55 #define CONFIG_SYS_NS16550_COM1         0x01c20000
  56 #define CONFIG_SYS_NS16550_CLK          CONFIG_SYS_HZ_CLOCK
  57 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  58 #define CONFIG_CONS_INDEX               1
  59 #define CONFIG_BAUDRATE                 115200
  60
  61 /* Network Configuration */
  62 #define CONFIG_DRIVER_TI_EMAC
  63 #define CONFIG_EMAC_MDIO_PHY_NUM        0
  64 #define CONFIG_SYS_EMAC_TI_CLKDIV       0xa9    /* 1MHz */
  65 #define CONFIG_MII
  66 #define CONFIG_BOOTP_DEFAULT
  67 #define CONFIG_BOOTP_DNS
  68 #define CONFIG_BOOTP_DNS2
  69 #define CONFIG_BOOTP_SEND_HOSTNAME
  70 #define CONFIG_NET_RETRY_COUNT  10
  71 #define CONFIG_CMD_MII
  72 #define CONFIG_SYS_DCACHE_OFF
  73 #define CONFIG_RESET_PHY_R
  74
  75 /* I2C */
  76 #define CONFIG_HARD_I2C
  77 #define CONFIG_DRIVER_DAVINCI_I2C
  78 #define CONFIG_SYS_I2C_SPEED            400000
  79 #define CONFIG_SYS_I2C_SLAVE            0x10    /* SMBus host address */
  80
  81 /* NAND: socketed, two chipselects, normally 2 GBytes */
  82 #define CONFIG_NAND_DAVINCI
  83 #define CONFIG_SYS_NAND_CS              2
  84 #define CONFIG_SYS_NAND_USE_FLASH_BBT
  85 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  86 #define CONFIG_SYS_NAND_PAGE_2K
  87
  88 #define CONFIG_SYS_NAND_LARGEPAGE
  89 #define CONFIG_SYS_NAND_BASE_LIST       { 0x02000000, }
  90 /* socket has two chipselects, nCE0 gated by address BIT(14) */
  91 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  92
  93 /* SPI support */
  94 #define CONFIG_SPI
  95 #define CONFIG_SPI_FLASH
  96 #define CONFIG_SPI_FLASH_STMICRO
  97 #define CONFIG_DAVINCI_SPI
  98 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
  99 #define CONFIG_SYS_SPI_CLK              davinci_clk_get(SPI_PLLDIV)
 100 #define CONFIG_SF_DEFAULT_SPEED         3000000
 101 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
 102 #define CONFIG_CMD_SF
 103
 104 /* SD/MMC */
 105 #define CONFIG_MMC
 106 #define CONFIG_GENERIC_MMC
 107 #define CONFIG_DAVINCI_MMC
 108 #define CONFIG_MMC_MBLOCK
 109
 110 /* U-Boot command configuration */
 111 #include <config_cmd_default.h>
 112
 113 #define CONFIG_CMD_BDI
 114 #undef CONFIG_CMD_FLASH
 115 #undef CONFIG_CMD_FPGA
 116 #undef CONFIG_CMD_SETGETDCR
 117 #define CONFIG_CMD_ASKENV
 118 #define CONFIG_CMD_CACHE
 119 #define CONFIG_CMD_DHCP
 120 #define CONFIG_CMD_I2C
 121 #define CONFIG_CMD_PING
 122 #define CONFIG_CMD_SAVES
 123
 124 #ifdef CONFIG_CMD_BDI
 125 #define CONFIG_CLOCKS
 126 #endif
 127
 128 #ifdef CONFIG_MMC
 129 #define CONFIG_DOS_PARTITION
 130 #define CONFIG_CMD_EXT2
 131 #define CONFIG_CMD_FAT
 132 #define CONFIG_CMD_MMC
 133 #endif
 134
 135 #ifdef CONFIG_NAND_DAVINCI
 136 #define CONFIG_CMD_MTDPARTS
 137 #define CONFIG_MTD_PARTITIONS
 138 #define CONFIG_MTD_DEVICE
 139 #define CONFIG_CMD_NAND
 140 #define CONFIG_CMD_UBI
 141 #define CONFIG_CMD_UBIFS
 142 #define CONFIG_RBTREE
 143 #define CONFIG_LZO
 144 #endif
 145
 146 #define CONFIG_CRC32_VERIFY
 147 #define CONFIG_MX_CYCLIC
 148
 149 /* U-Boot general configuration */
 150 #undef CONFIG_USE_IRQ                           /* No IRQ/FIQ in U-Boot */
 151 #define CONFIG_BOOTFILE         "uImage"        /* Boot file name */
 152 #define CONFIG_SYS_PROMPT       "cam_enc_4xx> " /* Monitor Command Prompt */
 153 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size  */
 154 #define CONFIG_SYS_PBSIZE                       /* Print buffer size */ \
 155                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 156 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 157 #define CONFIG_SYS_HUSH_PARSER
 158 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 159 #define CONFIG_SYS_LONGHELP
 160
 161 #define CONFIG_MENU
 162 #define CONFIG_MENU_SHOW
 163 #define CONFIG_FIT
 164 #define CONFIG_CMD_PXE
 165 #define CONFIG_BOARD_IMG_ADDR_R 0x80000000
 166
 167 #ifdef CONFIG_NAND_DAVINCI
 168 #define CONFIG_ENV_SIZE                 (16 << 10)
 169 #define CONFIG_ENV_IS_IN_NAND
 170 #define CONFIG_ENV_OFFSET               0x180000
 171 #define CONFIG_ENV_OFFSET_REDUND        0x1c0000
 172 #define CONFIG_ENV_RANGE                0x020000
 173 #undef CONFIG_ENV_IS_IN_FLASH
 174 #endif
 175
 176 #if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
 177 #define CONFIG_CMD_ENV
 178 #define CONFIG_SYS_MMC_ENV_DEV  0
 179 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
 180 #define CONFIG_ENV_OFFSET       (51 << 9)       /* Sector 51 */
 181 #define CONFIG_ENV_IS_IN_MMC
 182 #undef CONFIG_ENV_IS_IN_FLASH
 183 #endif
 184
 185 #define CONFIG_BOOTDELAY        3
 186 /*
 187  * 24MHz InputClock / 15 prediv -> 1.6 MHz timer running
 188  * Timeout 1 second.
 189  */
 190 #define CONFIG_AIT_TIMER_TIMEOUT        0x186a00
 191
 192 #define CONFIG_CMDLINE_EDITING
 193 #define CONFIG_VERSION_VARIABLE
 194 #define CONFIG_TIMESTAMP
 195
 196 /* U-Boot memory configuration */
 197 #define CONFIG_STACKSIZE                (256 << 10)     /* 256 KiB */
 198 #define CONFIG_SYS_MALLOC_LEN           (1 << 20)       /* 1 MiB */
 199 #define CONFIG_SYS_MEMTEST_START        0x80000000      /* physical address */
 200 #define CONFIG_SYS_MEMTEST_END          0x81000000      /* test 16MB RAM */
 201
 202 /* Linux interfacing */
 203 #define CONFIG_CMDLINE_TAG
 204 #define CONFIG_SETUP_MEMORY_TAGS
 205 #define CONFIG_SYS_BARGSIZE     1024                    /* bootarg Size */
 206 #define CONFIG_SYS_LOAD_ADDR    0x80700000              /* kernel address */
 207
 208 #define MTDIDS_DEFAULT          "nand0=davinci_nand.0"
 209 #define MTDPARTS_DEFAULT                        \
 210         "mtdparts="                             \
 211                 "davinci_nand.0:"               \
 212                         "128k(spl),"            \
 213                         "384k(UBLheader),"      \
 214                         "1m(u-boot),"           \
 215                         "512k(env),"            \
 216                         "-(ubi)"
 217
 218 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 219 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
 220
 221 /* Defines for SPL */
 222 #define CONFIG_SPL
 223 #define CONFIG_SPL_NAND_SUPPORT
 224 #define CONFIG_SPL_NAND_SIMPLE
 225 #define CONFIG_SPL_NAND_LOAD
 226 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 227 #define CONFIG_SPL_SERIAL_SUPPORT
 228 #define CONFIG_SPL_POST_MEM_SUPPORT
 229 #define CONFIG_SPL_LDSCRIPT             "$(BOARDDIR)/u-boot-spl.lds"
 230 #define CONFIG_SPL_STACK                (0x00010000 + 0x7f00)
 231
 232 #define CONFIG_SPL_TEXT_BASE            0x0000020 /*CONFIG_SYS_SRAM_START*/
 233 #define CONFIG_SPL_MAX_SIZE             12320
 234
 235 #ifndef CONFIG_SPL_BUILD
 236 #define CONFIG_SYS_TEXT_BASE            0x81080000
 237 #endif
 238
 239 #define CONFIG_SYS_NAND_BASE            0x02000000
 240 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
 241                                         CONFIG_SYS_NAND_PAGE_SIZE)
 242
 243 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 244                                 24, 25, 26, 27, 28,                     \
 245                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 246                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 247                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 248                                 59, 60, 61, 62, 63 }
 249 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 250 #define CONFIG_SYS_NAND_ECCSIZE         0x200
 251 #define CONFIG_SYS_NAND_ECCBYTES        10
 252 #define CONFIG_SYS_NAND_OOBSIZE         64
 253 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 254
 255 /*
 256  * RBL searches from Block n (n = 1..24)
 257  * so we can define, how many UBL Headers
 258  * we can write before the real spl code
 259  */
 260 #define CONFIG_SYS_NROF_PAGES_NAND_SPL  6
 261
 262 #define CONFIG_SYS_NAND_U_BOOT_DST      0x81080000 /* u-boot TEXT_BASE */
 263 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 264
 265 /*
 266  * Post tests for memory testing
 267  */
 268 #define CONFIG_POST     CONFIG_SYS_POST_MEMORY
 269 #define _POST_WORD_ADDR 0x0
 270
 271 #define CONFIG_DISPLAY_BOARDINFO
 272
 273 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_STACK
 274
 275 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 276 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0xa0000
 277
 278 /* for UBL header */
 279 #define CONFIG_SYS_UBL_BLOCK            (CONFIG_SYS_NAND_PAGE_SIZE)
 280
 281 #define CONFIG_SYS_DM36x_PLL1_PLLM      0x55
 282 #define CONFIG_SYS_DM36x_PLL1_PREDIV    0x8005
 283 #define CONFIG_SYS_DM36x_PLL2_PLLM      0x09
 284 #define CONFIG_SYS_DM36x_PLL2_PREDIV    0x8000
 285 #define CONFIG_SYS_DM36x_PERI_CLK_CTRL  0x243F04FC
 286 #define CONFIG_SYS_DM36x_PLL1_PLLDIV1   0x801b
 287 #define CONFIG_SYS_DM36x_PLL1_PLLDIV2   0x8001
 288 /* POST DIV 680/2 = 340Mhz  -> MJCP and HDVICP bus interface clock */
 289 #define CONFIG_SYS_DM36x_PLL1_PLLDIV3   0x8001
 290 /*
 291  * POST DIV 680/4 = 170Mhz  -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
 292  * interface clk)
 293  */
 294 #define CONFIG_SYS_DM36x_PLL1_PLLDIV4   0x8003
 295 /* POST DIV 680/2 = 340Mhz  -> VPSS */
 296 #define CONFIG_SYS_DM36x_PLL1_PLLDIV5   0x8001
 297 /* POST DIV 680/9 = 75.6 Mhz -> VENC */
 298 #define CONFIG_SYS_DM36x_PLL1_PLLDIV6   0x8008
 299 /*
 300  * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
 301  * down to 340 Mhz)
 302  */
 303 #define CONFIG_SYS_DM36x_PLL1_PLLDIV7   0x8000
 304 /* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
 305 #define CONFIG_SYS_DM36x_PLL1_PLLDIV8   0x8006
 306 /* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
 307 #define CONFIG_SYS_DM36x_PLL1_PLLDIV9   0x801b
 308
 309 #define CONFIG_SYS_DM36x_PLL2_PLLDIV1   0x8011
 310 /* POST DIV 432/1=432 Mhz  -> ARM926/(HDVICP block) clk */
 311 #define CONFIG_SYS_DM36x_PLL2_PLLDIV2   0x8000
 312 #define CONFIG_SYS_DM36x_PLL2_PLLDIV3   0x8001
 313 /* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
 314 #define CONFIG_SYS_DM36x_PLL2_PLLDIV4   0x8014
 315 /* POST DIV 432/16=27 Mhz  -> VENC(For SD modes, requires) */
 316 #define CONFIG_SYS_DM36x_PLL2_PLLDIV5   0x800f
 317
 318 /*
 319  * READ LATENCY 7 (CL + 2)
 320  * CONFIG_PWRDNEN = 1
 321  * CONFIG_EXT_STRBEN = 1
 322  */
 323 #define CONFIG_SYS_DM36x_DDR2_DDRPHYCR  (0 \
 324         | DV_DDR_PHY_EXT_STRBEN \
 325         | DV_DDR_PHY_PWRDNEN \
 326         | (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
 327
 328 /*
 329  * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
 330  * T_RP  = (trp/DDR_CLK) - 1  = (12.5 / 2.941) - 1
 331  * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
 332  * T_WR  = (twr/DDR_CLK) - 1  = (15 / 2.941) - 1
 333  * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
 334  * T_RC  = (trc/DDR_CLK) - 1  = (57.5 / 2.941) - 1
 335  * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
 336  * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
 337  */
 338 #define CONFIG_SYS_DM36x_DDR2_SDTIMR    (0 \
 339         | (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
 340         | (4  << DV_DDR_SDTMR1_RP_SHIFT) \
 341         | (4  << DV_DDR_SDTMR1_RCD_SHIFT) \
 342         | (5  << DV_DDR_SDTMR1_WR_SHIFT) \
 343         | (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
 344         | (19 << DV_DDR_SDTMR1_RC_SHIFT) \
 345         | (2  << DV_DDR_SDTMR1_RRD_SHIFT) \
 346         | (2  << DV_DDR_SDTMR1_WTR_SHIFT))
 347
 348 /*
 349  * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
 350  * T_XP  = tCKE - 1 = 3 - 2
 351  * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
 352  * T_XSRD = txsrd - 1 = 200 - 1
 353  * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
 354  * T_CKE = tcke - 1     = 3 - 1
 355  */
 356 #define CONFIG_SYS_DM36x_DDR2_SDTIMR2   (0 \
 357         | (8  << DV_DDR_SDTMR2_RASMAX_SHIFT) \
 358         | (2  << DV_DDR_SDTMR2_XP_SHIFT) \
 359         | (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
 360         | (199 <<  DV_DDR_SDTMR2_XSRD_SHIFT) \
 361         | (2 <<  DV_DDR_SDTMR2_RTP_SHIFT) \
 362         | (2 <<  DV_DDR_SDTMR2_CKE_SHIFT))
 363
 364 /* PR_OLD_COUNT = 0xfe */
 365 #define CONFIG_SYS_DM36x_DDR2_PBBPR     0x000000FE
 366 /* refresh rate = 0x768 */
 367 #define CONFIG_SYS_DM36x_DDR2_SDRCR     0x00000768
 368
 369 #define CONFIG_SYS_DM36x_DDR2_SDBCR     (0 \
 370         | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
 371         | (3 << DV_DDR_SDCR_IBANK_SHIFT) \
 372         | (5 << DV_DDR_SDCR_CL_SHIFT) \
 373         | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)    \
 374         | (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
 375         | (1 << DV_DDR_SDCR_DDREN_SHIFT) \
 376         | (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT)    \
 377         | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
 378         | (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
 379         | (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
 380
 381 #define CONFIG_SYS_DM36x_AWCCR  0xff
 382 #define CONFIG_SYS_DM36x_AB1CR  0x40400204
 383 #define CONFIG_SYS_DM36x_AB2CR  0x04ca2650
 384
 385 /* All Video Inputs */
 386 #define CONFIG_SYS_DM36x_PINMUX0        0x00000000
 387 /*
 388  * All Video Outputs,
 389  * GPIO 86, 87 + 90 0x0000f030
 390  */
 391 #define CONFIG_SYS_DM36x_PINMUX1        0x00530002
 392 #define CONFIG_SYS_DM36x_PINMUX2        0x00001815
 393 /*
 394  * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
 395  * GPIO 25 0x60000000
 396  */
 397 #define CONFIG_SYS_DM36x_PINMUX3        0x9b5affff
 398 /*
 399  * MMC/SD0 instead of MS, SPI0
 400  * GPIO 34 0x0000c000
 401  */
 402 #define CONFIG_SYS_DM36x_PINMUX4        0x00002655
 403
 404 /*
 405  * Default environment settings
 406  */
 407 #define xstr(s) str(s)
 408 #define str(s)  #s
 409
 410 #define DVN4XX_UBOOT_ADDR_R_RAM         0x80000000
 411 /* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
 412 #define DVN4XX_UBOOT_ADDR_R_NAND_SPL    0x80000800
 413 /*
 414  * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
 415  * CONFIG_SYS_NAND_PAGE_SIZE))
 416  */
 417 #define DVN4XX_UBOOT_ADDR_R_UBOOT       0x80003800
 418
 419 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 420         "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0"             \
 421         "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0"                 \
 422         "load=tftp ${u_boot_addr_r} ${u-boot}\0"                        \
 423         "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0"                  \
 424         "writeheader=nandrbl rbl;nand erase 20000 ${pagesz};"           \
 425                 "nand write ${u_boot_addr_r} 20000 ${pagesz};"          \
 426                 "nandrbl uboot\0"                                       \
 427         "writenand_spl=nandrbl rbl;nand erase 0 3000;"                  \
 428                 "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL)        \
 429                 " 0 3000;nandrbl uboot\0"                               \
 430         "writeuboot=nandrbl uboot;"                                     \
 431                 "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "     \
 432                  xstr(CONFIG_SYS_NAND_U_BOOT_SIZE)                      \
 433                 ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT)          \
 434                 " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "               \
 435                 xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"                  \
 436         "update=run load writenand_spl writeuboot\0"                    \
 437         "bootcmd=run net_nfs\0"                                         \
 438         "rootpath=/opt/eldk-arm/arm\0"                                  \
 439         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
 440         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
 441         "netdev=eth0\0"                                                 \
 442         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 443         "addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0"  \
 444         "addcon=setenv bootargs ${bootargs} console=ttyS0,"             \
 445                 "${baudrate}n8\0"                                       \
 446         "addip=setenv bootargs ${bootargs} "                            \
 447                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 448                 ":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0"   \
 449         "rootpath=/opt/eldk-arm/arm\0"                                  \
 450         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 451                 "nfsroot=${serverip}:${rootpath}\0"                     \
 452         "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage \0"                  \
 453         "kernel_addr_r=80600000\0"                                      \
 454         "load_kernel=tftp ${kernel_addr_r} ${bootfile}\0"               \
 455         "ubi_load_kernel=ubi part ubi 2048;ubifsmount ${img_volume};"   \
 456                 "ubifsload ${kernel_addr_r} boot/uImage\0"              \
 457         "fit_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0"                \
 458         "img_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0"                \
 459         "img_file=" xstr(CONFIG_HOSTNAME) "/ait.itb\0"                  \
 460         "header_addr=20000\0"                                           \
 461         "img_writeheader=nandrbl rbl;"                                  \
 462                 "nand erase ${header_addr} ${pagesz};"                  \
 463                 "nand write ${img_addr_r} ${header_addr} ${pagesz};"    \
 464                 "nandrbl uboot\0"                                       \
 465         "img_writespl=nandrbl rbl;nand erase 0 3000;"                   \
 466                 "nand write ${img_addr_r} 0 3000;nandrbl uboot\0"       \
 467         "img_writeuboot=nandrbl uboot;"                                 \
 468                 "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "     \
 469                  xstr(CONFIG_SYS_NAND_U_BOOT_SIZE)                      \
 470                 ";nand write ${img_addr_r} "                            \
 471                 xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "                   \
 472                 xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"                  \
 473         "img_writedfenv=ubi part ubi 2048;"                             \
 474                 "ubi write ${img_addr_r} default ${filesize}\0"         \
 475         "img_volume=rootfs1\0"                                          \
 476         "img_writeramdisk=ubi part ubi 2048;ubifsmount ${img_volume};"  \
 477                 "ubi write ${img_addr_r} ${img_volume} ${filesize}\0"   \
 478         "load_img=tftp ${fit_addr_r} ${img_file}\0"                     \
 479         "net_nfs=run load_kernel; "                                     \
 480                 "run nfsargs addip addcon addmtd addmisc;"              \
 481                 "bootm ${kernel_addr_r}\0"                              \
 482         "ubi_ubi=run ubi_load_kernel; "                                 \
 483                 "run ubiargs addip addcon addmtd addmisc;"              \
 484                 "bootm ${kernel_addr_r}\0"                              \
 485         "ubiargs=setenv bootargs ubi.mtd=4,2048"                        \
 486                 " root=ubi0:${img_volume} rw rootfstype=ubifs\0"        \
 487         "app_reset=no\0"                                                \
 488         "dvn_app_vers=void\0"                                           \
 489         "dvn_boot_vers=void\0"                                          \
 490         "savenewvers=run savetmpparms restoreparms; saveenv;"           \
 491                 "run restoretmpparms\0"                                 \
 492         "savetmpparms=setenv y_ipaddr ${ipaddr};"                       \
 493                 "setenv y_netmask ${netmask};"                          \
 494                 "setenv y_serverip ${serverip};"                        \
 495                 "setenv y_gatewayip ${gatewayip}\0"                     \
 496         "saveparms=setenv x_ipaddr ${ipaddr};"                          \
 497                 "setenv x_netmask ${netmask};"                          \
 498                 "setenv x_serverip ${serverip};"                        \
 499                 "setenv x_gatewayip ${gatewayip}\0"                     \
 500         "restoreparms=setenv ipaddr ${x_ipaddr};"                       \
 501                 "setenv netmask ${x_netmask};"                          \
 502                 "setenv serverip ${x_serverip};"                        \
 503                 "setenv gatewayip ${x_gatewayip}\0"                     \
 504         "restoretmpparms=setenv ipaddr ${y_ipaddr};"                    \
 505                 "setenv netmask ${y_netmask};"                          \
 506                 "setenv serverip ${y_serverip};"                        \
 507                 "setenv gatewayip ${y_gatewayip}\0"                     \
 508         "\0"
 509
 510 /* USB Configuration */
 511 #define CONFIG_USB_DAVINCI
 512 #define CONFIG_MUSB_HCD
 513 #define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
 514                                 USBPHY_PHY24MHZ)
 515
 516 #define CONFIG_CMD_USB         /* include support for usb cmd */
 517 #define CONFIG_USB_STORAGE     /* MSC class support */
 518 #define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
 519 #define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
 520 #define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
 521
 522 #undef DAVINCI_DM365EVM
 523 #define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
 524 #define PINMUX4_USBDRVBUS_BITSET         0x2000
 525
 526 #endif /* __CONFIG_H */