include/configs/calimain.h

   1 /*
   2  * Copyright (C) 2011 OMICRON electronics GmbH
   3  *
   4  * Based on da850evm.h. Original Copyrights follow:
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * Board
  29  */
  30 #define CONFIG_DRIVER_TI_EMAC
  31 #define MACH_TYPE_CALIMAIN      3528
  32 #define CONFIG_MACH_TYPE        MACH_TYPE_CALIMAIN
  33
  34 /*
  35  * SoC Configuration
  36  */
  37 #define CONFIG_MACH_DAVINCI_CALIMAIN
  38 #define CONFIG_ARM926EJS                /* arm926ejs CPU core */
  39 #define CONFIG_SOC_DA8XX                /* TI DA8xx SoC */
  40 #define CONFIG_SOC_DA850                /* TI DA850 SoC */
  41 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  42 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  43 #define CONFIG_SYS_OSCIN_FREQ           calimain_get_osc_freq()
  44 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  45 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  46 #define CONFIG_SYS_HZ                   1000
  47 #define CONFIG_SYS_TEXT_BASE            0x60000000
  48 #define CONFIG_DA850_LOWLEVEL
  49 #define CONFIG_SYS_DA850_PLL_INIT
  50 #define CONFIG_SYS_DA850_DDR_INIT
  51 #define CONFIG_ARCH_CPU_INIT
  52 #define CONFIG_DA8XX_GPIO
  53 #define CONFIG_HW_WATCHDOG
  54 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
  55 #define CONFIG_SYS_WDT_PERIOD_LOW \
  56         (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
  57 #define CONFIG_SYS_WDT_PERIOD_HIGH      0x0
  58 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  59
  60 /*
  61  * PLL configuration
  62  */
  63 #define CONFIG_SYS_DV_CLKMODE          0
  64 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
  65 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
  66 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
  67 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
  68 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
  69 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
  70 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
  71 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
  72
  73 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
  74 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
  75 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
  76 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
  77
  78 #define CONFIG_SYS_DA850_PLL0_PLLM \
  79         ((calimain_get_osc_freq() == 25000000) ? 23 : 24)
  80 #define CONFIG_SYS_DA850_PLL1_PLLM \
  81         ((calimain_get_osc_freq() == 25000000) ? 20 : 21)
  82
  83 /*
  84  * DDR2 memory configuration
  85  */
  86 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  87                                         DV_DDR_PHY_EXT_STRBEN | \
  88                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  89
  90 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  91         (1 << DV_DDR_SDCR_DDR2EN_SHIFT) |       \
  92         (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |    \
  93         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  94         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  95         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  96         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  97         (0x3 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  98         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  99
 100 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
 101 #define CONFIG_SYS_DA850_DDR2_SDBCR2    0
 102
 103 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
 104         (16 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
 105         (1 << DV_DDR_SDTMR1_RP_SHIFT) |         \
 106         (1 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
 107         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
 108         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
 109         (7 << DV_DDR_SDTMR1_RC_SHIFT) |         \
 110         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
 111         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
 112
 113 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
 114         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
 115         (2 << DV_DDR_SDTMR2_XP_SHIFT) |         \
 116         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
 117         (18 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
 118         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
 119         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
 120         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
 121
 122 #define CONFIG_SYS_DA850_DDR2_SDRCR     0x000003FF
 123 #define CONFIG_SYS_DA850_DDR2_PBBPR     0x30
 124
 125 /*
 126  * Flash memory timing
 127  */
 128
 129 #define CONFIG_SYS_DA850_CS2CFG (       \
 130         DAVINCI_ABCR_WSETUP(2) |        \
 131         DAVINCI_ABCR_WSTROBE(5) |       \
 132         DAVINCI_ABCR_WHOLD(3) |         \
 133         DAVINCI_ABCR_RSETUP(1) |        \
 134         DAVINCI_ABCR_RSTROBE(14) |      \
 135         DAVINCI_ABCR_RHOLD(0) |         \
 136         DAVINCI_ABCR_TA(3) |            \
 137         DAVINCI_ABCR_ASIZE_16BIT)
 138
 139 /* single 64 MB NOR flash device connected to CS2 and CS3 */
 140 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
 141
 142 /*
 143  * Memory Info
 144  */
 145 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
 146 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 147 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
 148 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
 149
 150 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
 151         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
 152         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
 153         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
 154         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
 155         DAVINCI_SYSCFG_SUSPSRC_I2C)
 156
 157 /* memtest start addr */
 158 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
 159
 160 /* memtest will be run on 16MB */
 161 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + (16 << 20))
 162
 163 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
 164
 165 /*
 166  * Serial Driver info
 167  */
 168 #define CONFIG_SYS_NS16550
 169 #define CONFIG_SYS_NS16550_SERIAL
 170 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 171 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 172 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 173 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
 174 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
 175
 176 #define CONFIG_ENV_IS_IN_FLASH
 177 #define CONFIG_FLASH_CFI_DRIVER
 178 #define CONFIG_SYS_FLASH_CFI
 179 #define CONFIG_SYS_FLASH_PROTECTION
 180 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 181 #define CONFIG_SYS_MAX_FLASH_BANKS  1 /* max number of flash banks */
 182 #define CONFIG_SYS_FLASH_SECT_SZ    (128 << 10) /* 128KB */
 183 #define CONFIG_SYS_FLASH_BASE       DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 184 #define CONFIG_ENV_SECT_SIZE        CONFIG_SYS_FLASH_SECT_SZ
 185 #define CONFIG_ENV_ADDR \
 186         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
 187 #define CONFIG_ENV_SIZE             (128 << 10)
 188 #define CONFIG_ENV_ADDR_REDUND      (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 189 #define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
 190 #define PHYS_FLASH_SIZE             (64 << 20) /* Flash size 64MB */
 191 #define CONFIG_SYS_MAX_FLASH_SECT \
 192         ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
 193
 194 /*
 195  * Network & Ethernet Configuration
 196  */
 197 #ifdef CONFIG_DRIVER_TI_EMAC
 198 #define CONFIG_EMAC_MDIO_PHY_NUM        1
 199 #define CONFIG_MII
 200 #define CONFIG_BOOTP_DEFAULT
 201 #define CONFIG_BOOTP_DNS
 202 #define CONFIG_BOOTP_DNS2
 203 #define CONFIG_BOOTP_SEND_HOSTNAME
 204 #define CONFIG_NET_RETRY_COUNT  10
 205 #endif
 206
 207 /*
 208  * U-Boot general configuration
 209  */
 210 #define CONFIG_BOOTFILE        "uImage" /* Boot file name */
 211 #define CONFIG_SYS_PROMPT      "Calimain > " /* Command Prompt */
 212 #define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size  */
 213 #define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 214 #define CONFIG_SYS_MAXARGS     16 /* max number of command args */
 215 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 216 #define CONFIG_SYS_LOAD_ADDR   (PHYS_SDRAM_1 + 0x700000)
 217 #define CONFIG_LOADADDR        0xc0700000
 218 #define CONFIG_VERSION_VARIABLE
 219 #define CONFIG_AUTO_COMPLETE
 220 #define CONFIG_SYS_HUSH_PARSER
 221 #define CONFIG_CMDLINE_EDITING
 222 #define CONFIG_SYS_LONGHELP
 223 #define CONFIG_CRC32_VERIFY
 224 #define CONFIG_MX_CYCLIC
 225
 226 /*
 227  * Linux Information
 228  */
 229 #define LINUX_BOOT_PARAM_ADDR     (PHYS_SDRAM_1 + 0x100)
 230 #define CONFIG_CMDLINE_TAG
 231 #define CONFIG_REVISION_TAG
 232 #define CONFIG_SETUP_MEMORY_TAGS
 233 #define CONFIG_BOOTARGS           ""
 234 #define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
 235 #define CONFIG_BOOTDELAY          0
 236 #define CONFIG_ZERO_BOOTDELAY_CHECK   /* check for keypress on bootdelay==0 */
 237 #define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
 238 #define CONFIG_AUTOBOOT_KEYED
 239 #define CONFIG_AUTOBOOT_DELAY_STR "\x0d" /* press ENTER to interrupt BOOT */
 240 #define CONFIG_RESET_TO_RETRY
 241
 242 /*
 243  * Default environment settings
 244  * gpio0 = button, gpio1 = led green, gpio2 = led red
 245  * verify = n ... disable kernel checksum verification for faster booting
 246  */
 247 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 248         "tftpdir=calimero\0"                                            \
 249         "flashkernel=tftpboot $loadaddr $tftpdir/uImage; "              \
 250                 "erase 0x60800000 +0x400000; "                          \
 251                 "cp.b $loadaddr 0x60800000 $filesize\0"                 \
 252         "flashrootfs="                                                  \
 253                 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; "            \
 254                 "erase 0x60c00000 +0x2e00000; "                         \
 255                 "cp.b $loadaddr 0x60c00000 $filesize\0"                 \
 256         "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; "           \
 257                 "protect off all; "                                     \
 258                 "erase 0x60000000 +0x80000; "                           \
 259                 "cp.b $loadaddr 0x60000000 $filesize\0"                 \
 260         "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; "             \
 261                 "erase 0x60080000 +0x780000; "                          \
 262                 "cp.b $loadaddr 0x60080000 $filesize\0"                 \
 263         "erase_persistent=erase 0x63a00000 +0x600000;\0"                \
 264         "bootnor=setenv bootargs console=ttyS2,115200n8 "               \
 265                 "root=/dev/mtdblock3 rw rootfstype=jffs2 "              \
 266                 "rootwait ethaddr=$ethaddr; "                           \
 267                 "gpio c 1; gpio s 2; bootm 0x60800000\0"                \
 268         "bootrlk=gpio s 1; gpio s 2;"                                   \
 269                 "setenv bootargs console=ttyS2,115200n8 "               \
 270                 "ethaddr=$ethaddr; bootm 0x60080000\0"                  \
 271         "boottftp=setenv bootargs console=ttyS2,115200n8 "              \
 272                 "root=/dev/mtdblock3 rw rootfstype=jffs2 "              \
 273                 "rootwait ethaddr=$ethaddr; "                           \
 274                 "tftpboot $loadaddr $tftpdir/uImage;"                   \
 275                 "gpio c 1; gpio s 2; bootm $loadaddr\0"                 \
 276         "checkupdate=if test -n $update_flag; then "                    \
 277                 "echo Previous update failed - starting RLK; "          \
 278                 "run bootrlk; fi; "                                     \
 279                 "if test -n $initial_setup; then "                      \
 280                 "echo Running initial setup procedure; "                \
 281                 "sleep 1; run flashall; fi\0"                           \
 282         "product=accessory\0"                                           \
 283         "serial=XX12345\0"                                              \
 284         "checknor="                                                     \
 285                 "if gpio i 0; then run bootnor; fi;\0"                  \
 286         "checkrlk="                                                     \
 287                 "if gpio i 0; then run bootrlk; fi;\0"                  \
 288         "checkbutton="                                                  \
 289                 "run checknor; sleep 1;"                                \
 290                 "run checknor; sleep 1;"                                \
 291                 "run checknor; sleep 1;"                                \
 292                 "run checknor; sleep 1;"                                \
 293                 "run checknor;"                                         \
 294                 "gpio s 1; gpio s 2;"                                   \
 295                 "echo ---- Release button to boot RLK ----;"            \
 296                 "run checkrlk; sleep 1;"                                \
 297                 "run checkrlk; sleep 1;"                                \
 298                 "run checkrlk; sleep 1;"                                \
 299                 "run checkrlk; sleep 1;"                                \
 300                 "run checkrlk; sleep 1;"                                \
 301                 "run checkrlk;"                                         \
 302                 "echo ---- Factory reset requested ----;"               \
 303                 "gpio c 1;"                                             \
 304                 "setenv factory_reset true;"                            \
 305                 "saveenv;"                                              \
 306                 "run bootnor;\0"                                        \
 307         "flashall=run flashrlk;"                                        \
 308                 "run flashkernel;"                                      \
 309                 "run flashrootfs;"                                      \
 310                 "setenv erase_datafs true;"                             \
 311                 "setenv initial_setup;"                                 \
 312                 "saveenv;"                                              \
 313                 "run bootnor;\0"                                        \
 314         "verify=n\0"                                                    \
 315         "clearenv=protect off all;"                                     \
 316                 "erase 0x60040000 +0x40000;\0"                          \
 317         "bootlimit=3\0"                                                 \
 318         "altbootcmd=run bootrlk\0"
 319
 320 #define CONFIG_PREBOOT                  \
 321         "echo Version: $ver; "          \
 322         "echo Serial: $serial; "        \
 323         "echo MAC: $ethaddr; "          \
 324         "echo Product: $product; "      \
 325         "gpio c 1; gpio c 2;"
 326
 327 /*
 328  * U-Boot commands
 329  */
 330 #include <config_cmd_default.h>
 331 #define CONFIG_CMD_ENV
 332 #define CONFIG_CMD_ASKENV
 333 #define CONFIG_CMD_DHCP
 334 #define CONFIG_CMD_DIAG
 335 #define CONFIG_CMD_MII
 336 #define CONFIG_CMD_PING
 337 #define CONFIG_CMD_SAVES
 338 #define CONFIG_CMD_MEMORY
 339 #define CONFIG_CMD_GPIO
 340
 341 #ifndef CONFIG_DRIVER_TI_EMAC
 342 #undef CONFIG_CMD_NET
 343 #undef CONFIG_CMD_DHCP
 344 #undef CONFIG_CMD_MII
 345 #undef CONFIG_CMD_PING
 346 #endif
 347
 348 /* additions for new relocation code, must added to all boards */
 349 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 350 /* initial stack pointer in internal SRAM */
 351 #define CONFIG_SYS_INIT_SP_ADDR         (0x8001ff00)
 352
 353 #define CONFIG_BOOTCOUNT_LIMIT
 354 #define CONFIG_SYS_BOOTCOUNT_LE         /* Use little-endian accessors */
 355 #define CONFIG_SYS_BOOTCOUNT_ADDR       DAVINCI_RTC_BASE
 356
 357 #ifndef __ASSEMBLY__
 358 int calimain_get_osc_freq(void);
 359 #endif
 360
 361 #endif /* __CONFIG_H */