1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * esd vme8349 U-Boot configuration file
4 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
6 * (C) Copyright 2006-2010
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * reinhard.arlt@esd-electronics.de
10 * Based on the MPC8349EMDS config.
14 * vme8349 board configuration file.
21 * High Level Configuration Options
23 #define CONFIG_E300 1 /* E300 Family */
25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
26 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
29 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
31 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
34 #define CONFIG_SYS_IMMR 0xE0000000
36 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
37 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
38 #define CONFIG_SYS_MEMTEST_END 0x00100000
43 #define CONFIG_DDR_ECC /* only for ECC DDR module */
44 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
45 #define CONFIG_SPD_EEPROM
46 #define SPD_EEPROM_ADDRESS 0x54
47 #define CONFIG_SYS_READ_SPD vme8349_read_spd
48 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
51 * 32-bit data path mode.
53 * Please note that using this mode for devices with the real density of 64-bit
54 * effectively reduces the amount of available memory due to the effect of
55 * wrapping around while translating address to row/columns, for example in the
56 * 256MB module the upper 128MB get aliased with contents of the lower
57 * 128MB); normally this define should be used for devices with real 32-bit
60 #undef CONFIG_DDR_32BIT
62 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
63 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
64 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
65 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
66 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
67 #define CONFIG_DDR_2T_TIMING
68 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
74 * FLASH on the Local Bus
76 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
77 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
78 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
79 BR_PS_16 | /* 16bit */ \
80 BR_MS_GPCM | /* MSEL = GPCM */ \
83 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
93 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
94 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
96 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
97 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
102 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
105 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
106 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
108 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
109 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
111 #undef CONFIG_SYS_FLASH_CHECKSUM
112 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
117 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
118 #define CONFIG_SYS_RAMBOOT
120 #undef CONFIG_SYS_RAMBOOT
123 #define CONFIG_SYS_INIT_RAM_LOCK 1
124 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
125 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
127 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
128 GENERATED_GBL_DATA_SIZE)
129 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
131 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
132 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
135 * Local Bus LCRR and LBCR regs
136 * LCRR: no DLL bypass, Clock divider is 4
137 * External Local Bus rate is
138 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
140 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
141 #define CONFIG_SYS_LBC_LBCR 0x00000000
143 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
148 #define CONFIG_SYS_NS16550_SERIAL
149 #define CONFIG_SYS_NS16550_REG_SIZE 1
150 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
152 #define CONFIG_SYS_BAUDRATE_TABLE \
153 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
155 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
156 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
159 #define CONFIG_SYS_I2C
160 #define CONFIG_SYS_I2C_FSL
161 #define CONFIG_SYS_FSL_I2C_SPEED 400000
162 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
163 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
164 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
165 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
166 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
167 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
168 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
170 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
173 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
174 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
175 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
176 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
180 * Addresses are mapped 1-1.
182 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
183 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
184 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
185 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
186 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
187 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
188 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
189 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
190 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
192 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
193 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
194 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
195 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
196 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
197 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
198 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
199 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
200 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
202 #if defined(CONFIG_PCI)
204 #undef CONFIG_EEPRO100
207 #if !defined(CONFIG_PCI_PNP)
208 #define PCI_ENET0_IOADDR 0xFIXME
209 #define PCI_ENET0_MEMADDR 0xFIXME
210 #define PCI_IDSEL_NUMBER 0xFIXME
213 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
214 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
216 #endif /* CONFIG_PCI */
222 #if defined(CONFIG_TSEC_ENET)
224 #define CONFIG_GMII /* MII PHY management */
226 #define CONFIG_TSEC1_NAME "TSEC0"
228 #define CONFIG_TSEC2_NAME "TSEC1"
229 #define CONFIG_PHY_M88E1111
230 #define TSEC1_PHY_ADDR 0x08
231 #define TSEC2_PHY_ADDR 0x10
232 #define TSEC1_PHYIDX 0
233 #define TSEC2_PHYIDX 0
234 #define TSEC1_FLAGS TSEC_GIGABIT
235 #define TSEC2_FLAGS TSEC_GIGABIT
237 /* Options are: TSEC[0-1] */
238 #define CONFIG_ETHPRIME "TSEC0"
240 #endif /* CONFIG_TSEC_ENET */
245 #ifndef CONFIG_SYS_RAMBOOT
246 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
247 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
248 #define CONFIG_ENV_SIZE 0x2000
250 /* Address and size of Redundant Environment Sector */
251 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
252 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
255 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
256 #define CONFIG_ENV_SIZE 0x2000
259 #define CONFIG_LOADS_ECHO /* echo on for serial download */
260 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
265 #define CONFIG_BOOTP_BOOTFILESIZE
268 * Command line configuration.
270 #define CONFIG_SYS_RTC_BUS_NUM 0x01
271 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
272 #define CONFIG_RTC_RX8025
274 /* Pass Ethernet MAC to VxWorks */
275 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
277 #undef CONFIG_WATCHDOG /* watchdog disabled */
280 * Miscellaneous configurable options
282 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
285 * For booting Linux, the board info and command line data
286 * have to be in the first 256 MB of memory, since this is
287 * the maximum mapped by the Linux kernel during initialization.
289 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
291 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
293 #define CONFIG_SYS_HRCW_LOW (\
294 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
295 HRCWL_DDR_TO_SCB_CLK_1X1 |\
296 HRCWL_CSB_TO_CLKIN |\
298 HRCWL_CORE_TO_CSB_2X1)
300 #if defined(PCI_64BIT)
301 #define CONFIG_SYS_HRCW_HIGH (\
304 HRCWH_PCI1_ARBITER_ENABLE |\
305 HRCWH_PCI2_ARBITER_DISABLE |\
307 HRCWH_FROM_0X00000100 |\
308 HRCWH_BOOTSEQ_DISABLE |\
309 HRCWH_SW_WATCHDOG_DISABLE |\
310 HRCWH_ROM_LOC_LOCAL_16BIT |\
311 HRCWH_TSEC1M_IN_GMII |\
312 HRCWH_TSEC2M_IN_GMII)
314 #define CONFIG_SYS_HRCW_HIGH (\
317 HRCWH_PCI1_ARBITER_ENABLE |\
318 HRCWH_PCI2_ARBITER_ENABLE |\
320 HRCWH_FROM_0X00000100 |\
321 HRCWH_BOOTSEQ_DISABLE |\
322 HRCWH_SW_WATCHDOG_DISABLE |\
323 HRCWH_ROM_LOC_LOCAL_16BIT |\
324 HRCWH_TSEC1M_IN_GMII |\
325 HRCWH_TSEC2M_IN_GMII)
328 /* System IO Config */
329 #define CONFIG_SYS_SICRH 0
330 #define CONFIG_SYS_SICRL SICRL_LDP_A
332 #define CONFIG_SYS_HID0_INIT 0x000000000
333 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
334 HID0_ENABLE_INSTRUCTION_CACHE)
336 #define CONFIG_SYS_HID2 HID2_HBE
338 #define CONFIG_SYS_GPIO1_PRELIM
339 #define CONFIG_SYS_GPIO1_DIR 0x00100000
340 #define CONFIG_SYS_GPIO1_DAT 0x00100000
342 #define CONFIG_SYS_GPIO2_PRELIM
343 #define CONFIG_SYS_GPIO2_DIR 0x78900000
344 #define CONFIG_SYS_GPIO2_DAT 0x70100000
346 #define CONFIG_HIGH_BATS /* High BATs supported */
348 /* DDR @ 0x00000000 */
349 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
351 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
354 /* PCI @ 0x80000000 */
356 #define CONFIG_PCI_INDIRECT_BRIDGE
357 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
359 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
361 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
362 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
363 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
366 #define CONFIG_SYS_IBAT1L (0)
367 #define CONFIG_SYS_IBAT1U (0)
368 #define CONFIG_SYS_IBAT2L (0)
369 #define CONFIG_SYS_IBAT2U (0)
372 #ifdef CONFIG_MPC83XX_PCI2
373 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
375 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
377 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
378 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
379 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
382 #define CONFIG_SYS_IBAT3L (0)
383 #define CONFIG_SYS_IBAT3U (0)
384 #define CONFIG_SYS_IBAT4L (0)
385 #define CONFIG_SYS_IBAT4U (0)
388 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
389 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
390 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
391 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
394 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
395 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
397 #if (CONFIG_SYS_DDR_SIZE == 512)
398 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
399 BATL_PP_RW | BATL_MEMCOHERENCE)
400 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
401 BATU_BL_256M | BATU_VS | BATU_VP)
403 #define CONFIG_SYS_IBAT7L (0)
404 #define CONFIG_SYS_IBAT7U (0)
407 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
408 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
409 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
410 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
411 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
412 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
413 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
414 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
415 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
416 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
417 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
418 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
419 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
420 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
421 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
422 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
424 #if defined(CONFIG_CMD_KGDB)
425 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
429 * Environment Configuration
431 #define CONFIG_ENV_OVERWRITE
433 #if defined(CONFIG_TSEC_ENET)
434 #define CONFIG_HAS_ETH0
435 #define CONFIG_HAS_ETH1
438 #define CONFIG_HOSTNAME "VME8349"
439 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
440 #define CONFIG_BOOTFILE "uImage"
442 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
444 #define CONFIG_EXTRA_ENV_SETTINGS \
446 "hostname=vme8349\0" \
447 "nfsargs=setenv bootargs root=/dev/nfs rw " \
448 "nfsroot=${serverip}:${rootpath}\0" \
449 "ramargs=setenv bootargs root=/dev/ram rw\0" \
450 "addip=setenv bootargs ${bootargs} " \
451 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
452 ":${hostname}:${netdev}:off panic=1\0" \
453 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
454 "flash_nfs=run nfsargs addip addtty;" \
455 "bootm ${kernel_addr}\0" \
456 "flash_self=run ramargs addip addtty;" \
457 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
458 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
460 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
461 "update=protect off fff00000 fff3ffff; " \
462 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
463 "upd=run load update\0" \
465 "fdtfile=vme8349.dtb\0" \
468 #define CONFIG_NFSBOOTCOMMAND \
469 "setenv bootargs root=/dev/nfs rw " \
470 "nfsroot=$serverip:$rootpath " \
471 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
473 "console=$consoledev,$baudrate $othbootargs;" \
474 "tftp $loadaddr $bootfile;" \
475 "tftp $fdtaddr $fdtfile;" \
476 "bootm $loadaddr - $fdtaddr"
478 #define CONFIG_RAMBOOTCOMMAND \
479 "setenv bootargs root=/dev/ram rw " \
480 "console=$consoledev,$baudrate $othbootargs;" \
481 "tftp $ramdiskaddr $ramdiskfile;" \
482 "tftp $loadaddr $bootfile;" \
483 "tftp $fdtaddr $fdtfile;" \
484 "bootm $loadaddr $ramdiskaddr $fdtaddr"
486 #define CONFIG_BOOTCOMMAND "run flash_self"
489 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
490 unsigned char *buffer, int len);
493 #endif /* __CONFIG_H */