1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * esd vme8349 U-Boot configuration file
4 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
6 * (C) Copyright 2006-2010
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * reinhard.arlt@esd-electronics.de
10 * Based on the MPC8349EMDS config.
14 * vme8349 board configuration file.
21 * High Level Configuration Options
23 #define CONFIG_E300 1 /* E300 Family */
25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
26 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
28 #define CONFIG_SYS_IMMR 0xE0000000
30 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
31 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
32 #define CONFIG_SYS_MEMTEST_END 0x00100000
37 #define CONFIG_DDR_ECC /* only for ECC DDR module */
38 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
39 #define CONFIG_SPD_EEPROM
40 #define SPD_EEPROM_ADDRESS 0x54
41 #define CONFIG_SYS_READ_SPD vme8349_read_spd
42 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
45 * 32-bit data path mode.
47 * Please note that using this mode for devices with the real density of 64-bit
48 * effectively reduces the amount of available memory due to the effect of
49 * wrapping around while translating address to row/columns, for example in the
50 * 256MB module the upper 128MB get aliased with contents of the lower
51 * 128MB); normally this define should be used for devices with real 32-bit
54 #undef CONFIG_DDR_32BIT
56 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
57 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
58 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
59 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
60 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
61 #define CONFIG_DDR_2T_TIMING
62 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
68 * FLASH on the Local Bus
70 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
71 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
74 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
77 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
78 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
80 #undef CONFIG_SYS_FLASH_CHECKSUM
81 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
82 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
84 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
86 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
87 #define CONFIG_SYS_RAMBOOT
89 #undef CONFIG_SYS_RAMBOOT
92 #define CONFIG_SYS_INIT_RAM_LOCK 1
93 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
94 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
96 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
97 GENERATED_GBL_DATA_SIZE)
98 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
100 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
101 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
104 * Local Bus LCRR and LBCR regs
105 * LCRR: no DLL bypass, Clock divider is 4
106 * External Local Bus rate is
107 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
109 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
110 #define CONFIG_SYS_LBC_LBCR 0x00000000
112 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
117 #define CONFIG_SYS_NS16550_SERIAL
118 #define CONFIG_SYS_NS16550_REG_SIZE 1
119 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
121 #define CONFIG_SYS_BAUDRATE_TABLE \
122 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
124 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
125 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
128 #define CONFIG_SYS_I2C
129 #define CONFIG_SYS_I2C_FSL
130 #define CONFIG_SYS_FSL_I2C_SPEED 400000
131 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
132 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
133 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
134 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
135 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
136 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
137 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
139 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
142 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
143 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
144 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
145 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
149 * Addresses are mapped 1-1.
151 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
152 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
153 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
154 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
155 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
156 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
157 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
158 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
159 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
161 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
162 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
163 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
164 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
165 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
166 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
167 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
168 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
169 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
171 #if defined(CONFIG_PCI)
173 #undef CONFIG_EEPRO100
176 #if !defined(CONFIG_PCI_PNP)
177 #define PCI_ENET0_IOADDR 0xFIXME
178 #define PCI_ENET0_MEMADDR 0xFIXME
179 #define PCI_IDSEL_NUMBER 0xFIXME
182 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
183 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
185 #endif /* CONFIG_PCI */
191 #if defined(CONFIG_TSEC_ENET)
193 #define CONFIG_GMII /* MII PHY management */
195 #define CONFIG_TSEC1_NAME "TSEC0"
197 #define CONFIG_TSEC2_NAME "TSEC1"
198 #define CONFIG_PHY_M88E1111
199 #define TSEC1_PHY_ADDR 0x08
200 #define TSEC2_PHY_ADDR 0x10
201 #define TSEC1_PHYIDX 0
202 #define TSEC2_PHYIDX 0
203 #define TSEC1_FLAGS TSEC_GIGABIT
204 #define TSEC2_FLAGS TSEC_GIGABIT
206 /* Options are: TSEC[0-1] */
207 #define CONFIG_ETHPRIME "TSEC0"
209 #endif /* CONFIG_TSEC_ENET */
214 #ifndef CONFIG_SYS_RAMBOOT
215 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
216 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
217 #define CONFIG_ENV_SIZE 0x2000
219 /* Address and size of Redundant Environment Sector */
220 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
221 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
224 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
225 #define CONFIG_ENV_SIZE 0x2000
228 #define CONFIG_LOADS_ECHO /* echo on for serial download */
229 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
234 #define CONFIG_BOOTP_BOOTFILESIZE
237 * Command line configuration.
239 #define CONFIG_SYS_RTC_BUS_NUM 0x01
240 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
241 #define CONFIG_RTC_RX8025
243 /* Pass Ethernet MAC to VxWorks */
244 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
246 #undef CONFIG_WATCHDOG /* watchdog disabled */
249 * Miscellaneous configurable options
251 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
254 * For booting Linux, the board info and command line data
255 * have to be in the first 256 MB of memory, since this is
256 * the maximum mapped by the Linux kernel during initialization.
258 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
260 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
262 /* System IO Config */
263 #define CONFIG_SYS_SICRH 0
264 #define CONFIG_SYS_SICRL SICRL_LDP_A
266 #define CONFIG_SYS_GPIO1_PRELIM
267 #define CONFIG_SYS_GPIO1_DIR 0x00100000
268 #define CONFIG_SYS_GPIO1_DAT 0x00100000
270 #define CONFIG_SYS_GPIO2_PRELIM
271 #define CONFIG_SYS_GPIO2_DIR 0x78900000
272 #define CONFIG_SYS_GPIO2_DAT 0x70100000
275 #define CONFIG_PCI_INDIRECT_BRIDGE
278 #if defined(CONFIG_CMD_KGDB)
279 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
283 * Environment Configuration
285 #define CONFIG_ENV_OVERWRITE
287 #if defined(CONFIG_TSEC_ENET)
288 #define CONFIG_HAS_ETH0
289 #define CONFIG_HAS_ETH1
292 #define CONFIG_HOSTNAME "VME8349"
293 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
294 #define CONFIG_BOOTFILE "uImage"
296 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
298 #define CONFIG_EXTRA_ENV_SETTINGS \
300 "hostname=vme8349\0" \
301 "nfsargs=setenv bootargs root=/dev/nfs rw " \
302 "nfsroot=${serverip}:${rootpath}\0" \
303 "ramargs=setenv bootargs root=/dev/ram rw\0" \
304 "addip=setenv bootargs ${bootargs} " \
305 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
306 ":${hostname}:${netdev}:off panic=1\0" \
307 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
308 "flash_nfs=run nfsargs addip addtty;" \
309 "bootm ${kernel_addr}\0" \
310 "flash_self=run ramargs addip addtty;" \
311 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
312 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
314 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
315 "update=protect off fff00000 fff3ffff; " \
316 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
317 "upd=run load update\0" \
319 "fdtfile=vme8349.dtb\0" \
322 #define CONFIG_NFSBOOTCOMMAND \
323 "setenv bootargs root=/dev/nfs rw " \
324 "nfsroot=$serverip:$rootpath " \
325 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
327 "console=$consoledev,$baudrate $othbootargs;" \
328 "tftp $loadaddr $bootfile;" \
329 "tftp $fdtaddr $fdtfile;" \
330 "bootm $loadaddr - $fdtaddr"
332 #define CONFIG_RAMBOOTCOMMAND \
333 "setenv bootargs root=/dev/ram rw " \
334 "console=$consoledev,$baudrate $othbootargs;" \
335 "tftp $ramdiskaddr $ramdiskfile;" \
336 "tftp $loadaddr $bootfile;" \
337 "tftp $fdtaddr $fdtfile;" \
338 "bootm $loadaddr $ramdiskaddr $fdtaddr"
340 #define CONFIG_BOOTCOMMAND "run flash_self"
343 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
344 unsigned char *buffer, int len);
347 #endif /* __CONFIG_H */