include/configs/caddy2.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * esd vme8349 U-Boot configuration file
   4  * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
   5  *
   6  * (C) Copyright 2006-2010
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * reinhard.arlt@esd-electronics.de
  10  * Based on the MPC8349EMDS config.
  11  */
  12
  13 /*
  14  * vme8349 board configuration file.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_E300             1       /* E300 Family */
  24
  25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  26 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  27
  28 #undef CONFIG_SYS_DRAM_TEST                     /* memory test, takes time */
  29
  30 /*
  31  * DDR Setup
  32  */
  33 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  34 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  35 #define CONFIG_SPD_EEPROM
  36 #define SPD_EEPROM_ADDRESS              0x54
  37 #define CONFIG_SYS_READ_SPD             vme8349_read_spd
  38 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* esd; Fsl board uses CS2/CS3 */
  39
  40 /*
  41  * 32-bit data path mode.
  42  *
  43  * Please note that using this mode for devices with the real density of 64-bit
  44  * effectively reduces the amount of available memory due to the effect of
  45  * wrapping around while translating address to row/columns, for example in the
  46  * 256MB module the upper 128MB get aliased with contents of the lower
  47  * 128MB); normally this define should be used for devices with real 32-bit
  48  * data path.
  49  */
  50 #undef CONFIG_DDR_32BIT
  51
  52 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* DDR is sys memory*/
  53 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  54                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  55 #define CONFIG_DDR_2T_TIMING
  56 #define CONFIG_SYS_DDRCDR               (DDRCDR_DHC_EN \
  57                                         | DDRCDR_ODT \
  58                                         | DDRCDR_Q_DRN)
  59                                         /* 0x80080001 */
  60
  61 /*
  62  * FLASH on the Local Bus
  63  */
  64 #define CONFIG_SYS_FLASH_BASE           0xffc00000      /* start of FLASH   */
  65 #define CONFIG_SYS_FLASH_SIZE           4               /* flash size in MB */
  66
  67
  68 #define CONFIG_SYS_WINDOW1_BASE         0xf0000000
  69
  70
  71 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  72 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device*/
  73
  74 #undef CONFIG_SYS_FLASH_CHECKSUM
  75 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase TO (ms) */
  76 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write TO (ms) */
  77
  78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  79
  80 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  81 #define CONFIG_SYS_RAMBOOT
  82 #else
  83 #undef CONFIG_SYS_RAMBOOT
  84 #endif
  85
  86 #define CONFIG_SYS_INIT_RAM_LOCK        1
  87 #define CONFIG_SYS_INIT_RAM_ADDR        0xF7000000      /* Initial RAM addr */
  88 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* size */
  89
  90 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  91                                          GENERATED_GBL_DATA_SIZE)
  92 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  93
  94 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB */
  95 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Malloc size */
  96
  97 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
  98
  99 /*
 100  * Serial Port
 101  */
 102 #define CONFIG_SYS_NS16550_SERIAL
 103 #define CONFIG_SYS_NS16550_REG_SIZE     1
 104 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 105
 106 #define CONFIG_SYS_BAUDRATE_TABLE  \
 107                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 108
 109 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR + 0x4500)
 110 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR + 0x4600)
 111
 112 /* I2C */
 113 #define CONFIG_SYS_I2C
 114 #define CONFIG_SYS_I2C_FSL
 115 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 116 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 117 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 118 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 119 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 120 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 121 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 122 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 123
 124 #define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
 125
 126 /* TSEC */
 127 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 128 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 129 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 130 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 131
 132 /*
 133  * General PCI
 134  * Addresses are mapped 1-1.
 135  */
 136 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 137 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 138 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 139 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 140 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 141 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 142 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 143 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 144 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 145
 146 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 147 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 148 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 149 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 150 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 151 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 152 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 153 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 154 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 155
 156 #if defined(CONFIG_PCI)
 157
 158 #undef CONFIG_TULIP
 159
 160 #if !defined(CONFIG_PCI_PNP)
 161         #define PCI_ENET0_IOADDR        0xFIXME
 162         #define PCI_ENET0_MEMADDR       0xFIXME
 163         #define PCI_IDSEL_NUMBER        0xFIXME
 164 #endif
 165
 166 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 167 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 168
 169 #endif  /* CONFIG_PCI */
 170
 171 /*
 172  * TSEC configuration
 173  */
 174
 175 #if defined(CONFIG_TSEC_ENET)
 176
 177 #define CONFIG_GMII                     /* MII PHY management */
 178 #define CONFIG_TSEC1
 179 #define CONFIG_TSEC1_NAME       "TSEC0"
 180 #define CONFIG_TSEC2
 181 #define CONFIG_TSEC2_NAME       "TSEC1"
 182 #define CONFIG_PHY_M88E1111
 183 #define TSEC1_PHY_ADDR          0x08
 184 #define TSEC2_PHY_ADDR          0x10
 185 #define TSEC1_PHYIDX            0
 186 #define TSEC2_PHYIDX            0
 187 #define TSEC1_FLAGS             TSEC_GIGABIT
 188 #define TSEC2_FLAGS             TSEC_GIGABIT
 189
 190 /* Options are: TSEC[0-1] */
 191 #define CONFIG_ETHPRIME         "TSEC0"
 192
 193 #endif  /* CONFIG_TSEC_ENET */
 194
 195 /*
 196  * Environment
 197  */
 198 #ifndef CONFIG_SYS_RAMBOOT
 199 /* Address and size of Redundant Environment Sector     */
 200 #endif
 201
 202 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 203 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 204
 205 /*
 206  * BOOTP options
 207  */
 208 #define CONFIG_BOOTP_BOOTFILESIZE
 209
 210 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 211 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 212
 213 /* Pass Ethernet MAC to VxWorks */
 214 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x000043f0
 215
 216 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 217
 218 /*
 219  * Miscellaneous configurable options
 220  */
 221 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 222
 223 /*
 224  * For booting Linux, the board info and command line data
 225  * have to be in the first 256 MB of memory, since this is
 226  * the maximum mapped by the Linux kernel during initialization.
 227  */
 228 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Init Memory map for Linux*/
 229
 230 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 231
 232 /* System IO Config */
 233 #define CONFIG_SYS_SICRH 0
 234 #define CONFIG_SYS_SICRL SICRL_LDP_A
 235
 236 #define CONFIG_SYS_GPIO1_PRELIM
 237 #define CONFIG_SYS_GPIO1_DIR    0x00100000
 238 #define CONFIG_SYS_GPIO1_DAT    0x00100000
 239
 240 #define CONFIG_SYS_GPIO2_PRELIM
 241 #define CONFIG_SYS_GPIO2_DIR    0x78900000
 242 #define CONFIG_SYS_GPIO2_DAT    0x70100000
 243
 244 #ifdef CONFIG_PCI
 245 #define CONFIG_PCI_INDIRECT_BRIDGE
 246 #endif
 247
 248 #if defined(CONFIG_CMD_KGDB)
 249 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 250 #endif
 251
 252 /*
 253  * Environment Configuration
 254  */
 255 #define CONFIG_ENV_OVERWRITE
 256
 257 #if defined(CONFIG_TSEC_ENET)
 258 #define CONFIG_HAS_ETH0
 259 #define CONFIG_HAS_ETH1
 260 #endif
 261
 262 #define CONFIG_HOSTNAME         "VME8349"
 263 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 264 #define CONFIG_BOOTFILE         "uImage"
 265
 266 #define CONFIG_LOADADDR         800000  /* def location for tftp and bootm */
 267
 268 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 269         "netdev=eth0\0"                                                 \
 270         "hostname=vme8349\0"                                            \
 271         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 272                 "nfsroot=${serverip}:${rootpath}\0"                     \
 273         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 274         "addip=setenv bootargs ${bootargs} "                            \
 275                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 276                 ":${hostname}:${netdev}:off panic=1\0"                  \
 277         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 278         "flash_nfs=run nfsargs addip addtty;"                           \
 279                 "bootm ${kernel_addr}\0"                                \
 280         "flash_self=run ramargs addip addtty;"                          \
 281                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 282         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 283                 "bootm\0"                                               \
 284         "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"              \
 285         "update=protect off fff00000 fff3ffff; "                        \
 286                 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
 287         "upd=run load update\0"                                         \
 288         "fdtaddr=780000\0"                                              \
 289         "fdtfile=vme8349.dtb\0"                                         \
 290         ""
 291
 292 #define CONFIG_NFSBOOTCOMMAND                                           \
 293         "setenv bootargs root=/dev/nfs rw "                             \
 294                 "nfsroot=$serverip:$rootpath "                          \
 295                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 296                                                         "$netdev:off "  \
 297                 "console=$consoledev,$baudrate $othbootargs;"           \
 298         "tftp $loadaddr $bootfile;"                                     \
 299         "tftp $fdtaddr $fdtfile;"                                       \
 300         "bootm $loadaddr - $fdtaddr"
 301
 302 #define CONFIG_RAMBOOTCOMMAND                                           \
 303         "setenv bootargs root=/dev/ram rw "                             \
 304                 "console=$consoledev,$baudrate $othbootargs;"           \
 305         "tftp $ramdiskaddr $ramdiskfile;"                               \
 306         "tftp $loadaddr $bootfile;"                                     \
 307         "tftp $fdtaddr $fdtfile;"                                       \
 308         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 309
 310 #define CONFIG_BOOTCOMMAND      "run flash_self"
 311
 312 #ifndef __ASSEMBLY__
 313 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
 314                      unsigned char *buffer, int len);
 315 #endif
 316
 317 #endif  /* __CONFIG_H */