include/configs/brppt1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * brtpp1.h
   4  *
   5  * specific parts for B&R T-Series Motherboard
   6  *
   7  * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
   8  * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
   9  */
  10
  11 #ifndef __CONFIG_BRPPT1_H__
  12 #define __CONFIG_BRPPT1_H__
  13
  14 #include <configs/bur_cfg_common.h>
  15 #include <configs/bur_am335x_common.h>
  16 #include <linux/stringify.h>
  17 /* ------------------------------------------------------------------------- */
  18 /* memory */
  19 #define CONFIG_SYS_BOOTM_LEN            SZ_32M
  20
  21 /* Clock Defines */
  22 #define V_OSCK                          26000000  /* Clock output from T2 */
  23 #define V_SCLK                          (V_OSCK)
  24
  25 #define CONFIG_POWER_TPS65217
  26
  27 /*#define CONFIG_MACH_TYPE              3589*/
  28 #define CONFIG_MACH_TYPE                0xFFFFFFFF /* TODO: check with kernel*/
  29
  30 /*
  31  * When we have NAND flash we expect to be making use of mtdparts,
  32  * both for ease of use in U-Boot and for passing information on to
  33  * the Linux kernel.
  34  */
  35
  36 #ifdef CONFIG_SPL_OS_BOOT
  37 #define CONFIG_SYS_SPL_ARGS_ADDR                0x80F80000
  38
  39 /* RAW SD card / eMMC */
  40 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900   /* address 0x120000 */
  41 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x80    /* address 0x10000 */
  42 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  0x80    /* 64KiB */
  43
  44 /* NAND */
  45 #ifdef CONFIG_MTD_RAW_NAND
  46 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS         0x140000
  47 #endif /* CONFIG_MTD_RAW_NAND */
  48 #endif /* CONFIG_SPL_OS_BOOT */
  49
  50 #ifdef CONFIG_MTD_RAW_NAND
  51 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  52 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
  53 #endif /* CONFIG_MTD_RAW_NAND */
  54
  55 #ifdef CONFIG_MTD_RAW_NAND
  56 #define NANDTGTS \
  57 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  58 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  59 "cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \
  60 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
  61 "nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \
  62         "root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \
  63 "b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \
  64         "run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
  65 "b_tgts_std=usb0 nand net\0" \
  66 "b_tgts_rcy=net usb0 nand\0" \
  67 "b_tgts_pme=usb0 nand net\0"
  68 #else
  69 #define NANDTGTS ""
  70 #endif /* CONFIG_MTD_RAW_NAND */
  71
  72 #define MMCSPI_TGTS \
  73 "t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
  74         "b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \
  75 "b_t30lgcy#0=" \
  76         "load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \
  77         "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \
  78         "load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \
  79         "load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\
  80         "run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
  81 "t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
  82         "b_mode=${b_mode}\0" \
  83 "b_t30lgcy#1=" \
  84         "load ${loaddev}:1 ${loadaddr} zImage && " \
  85         "load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \
  86         "load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \
  87         "run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \
  88 "b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \
  89 "b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \
  90 "b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \
  91 "b_tgts_rcy=t30lgcy#1 usb0 net\0" \
  92 "b_tgts_pme=net usb0 mmc0 mmc1\0" \
  93 "loaddev=mmc 1\0"
  94
  95 #ifdef CONFIG_ENV_IS_IN_MMC
  96 #define MMCTGTS \
  97 MMCSPI_TGTS \
  98 "cfgscr=mw ${dtbaddr} 0;" \
  99 " mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \
 100 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
 101 #else
 102 #define MMCTGTS ""
 103 #endif /* CONFIG_MMC */
 104
 105 #ifdef CONFIG_SPI
 106 #define SPITGTS \
 107 MMCSPI_TGTS \
 108 "cfgscr=mw ${dtbaddr} 0;" \
 109 " sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \
 110 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
 111 #else
 112 #define SPITGTS ""
 113 #endif /* CONFIG_SPI */
 114
 115 #define LOAD_OFFSET(x)                  0x8##x
 116
 117 #ifndef CONFIG_SPL_BUILD
 118 #define CONFIG_EXTRA_ENV_SETTINGS \
 119 BUR_COMMON_ENV \
 120 "verify=no\0" \
 121 "autoload=0\0" \
 122 "scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \
 123 "cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \
 124 "dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \
 125 "loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \
 126 "ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \
 127 "console=ttyO0,115200n8\0" \
 128 "optargs=consoleblank=0 quiet panic=2\0" \
 129 "b_break=0\0" \
 130 "b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \
 131 "b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \
 132 MMCTGTS \
 133 SPITGTS \
 134 NANDTGTS \
 135 "b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
 136 " elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
 137 " else setenv b_tgts ${b_tgts_std}; fi\0" \
 138 "b_default=run b_deftgts; for target in ${b_tgts};"\
 139 " do echo \"### booting ${target} ###\"; run b_${target};" \
 140 " if test ${b_break} = 1; then; exit; fi; done\0"
 141 #endif /* !CONFIG_SPL_BUILD*/
 142
 143 #ifdef CONFIG_MTD_RAW_NAND
 144 /*
 145  * GPMC  block.  We support 1 device and the physical address to
 146  * access CS0 at is 0x8000000.
 147  */
 148 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 149 #define CONFIG_SYS_NAND_BASE            0x8000000
 150 /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
 151 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW
 152 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 153 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 154 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 155 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
 156                                         CONFIG_SYS_NAND_PAGE_SIZE)
 157 #define CONFIG_SYS_NAND_OOBSIZE         64
 158 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 159 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9, \
 160                                         10, 11, 12, 13, 14, 15, 16, 17, \
 161                                         18, 19, 20, 21, 22, 23, 24, 25, \
 162                                         26, 27, 28, 29, 30, 31, 32, 33, \
 163                                         34, 35, 36, 37, 38, 39, 40, 41, \
 164                                         42, 43, 44, 45, 46, 47, 48, 49, \
 165                                         50, 51, 52, 53, 54, 55, 56, 57, }
 166
 167 #define CONFIG_SYS_NAND_ECCSIZE         512
 168 #define CONFIG_SYS_NAND_ECCBYTES        14
 169
 170 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 171
 172 #define CONFIG_NAND_OMAP_GPMC_WSCFG     1
 173 #endif /* CONFIG_MTD_RAW_NAND */
 174
 175 #if defined(CONFIG_ENV_IS_IN_NAND)
 176 #define CONFIG_SYS_ENV_SECT_SIZE        CONFIG_ENV_SIZE
 177 #endif
 178
 179 #endif  /* ! __CONFIG_BRPPT1_H__ */