Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
[platform/kernel/u-boot.git] / include / configs / br4.h
1 /*
2  * U-boot - Configuration file for BR4 Appliance
3  *
4  * based on bf537-stamp.h
5  * Copyright (c) Switchfin Org. <dpn@switchfin.org>
6  */
7
8 #ifndef __CONFIG_BR4_H__
9 #define __CONFIG_BR4_H__
10
11 #include <asm/config-pre.h>
12
13
14 /*
15  * Processor Settings
16  */
17 #define CONFIG_BFIN_CPU             bf537-0.3
18 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
19
20
21 /*
22  * Clock Settings
23  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
24  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
25  */
26 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
27 #define CONFIG_CLKIN_HZ                 25000000
28 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
29 /*                                                1 = CLKIN / 2         */
30 #define CONFIG_CLKIN_HALF               0
31 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
32 /*                                                1 = bypass PLL        */
33 #define CONFIG_PLL_BYPASS               0
34 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
35 /* Values can range from 0-63 (where 0 means 64)                        */
36 #define CONFIG_VCO_MULT                 24
37 /* CCLK_DIV controls the core clock divider                             */
38 /* Values can be 1, 2, 4, or 8 ONLY                                     */
39 #define CONFIG_CCLK_DIV                 1
40 /* SCLK_DIV controls the system clock divider                           */
41 /* Values can range from 1-15                                           */
42 #define CONFIG_SCLK_DIV                 5
43
44
45 /*
46  * Memory Settings
47  */
48 #define CONFIG_MEM_ADD_WDTH     10
49 #define CONFIG_MEM_SIZE         64
50
51 #define CONFIG_EBIU_SDRRC_VAL   0x306
52 #define CONFIG_EBIU_SDGCTL_VAL  0x8091998d
53
54 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
55 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
56 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
57
58 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
59 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)
60
61
62 /*
63  * Network Settings
64  */
65 #ifndef __ADSPBF534__
66 #define ADI_CMDS_NETWORK        1
67 #define CONFIG_BFIN_MAC
68 #define CONFIG_NETCONSOLE
69 #endif
70 #define CONFIG_HOSTNAME         br4
71 #define CONFIG_TFTP_BLOCKSIZE   4404
72 /* Uncomment next line to use fixed MAC address */
73 /* #define CONFIG_ETHADDR       5c:38:1a:80:a7:00 */
74
75
76 /*
77  * Flash Settings
78  */
79 #define CONFIG_SYS_NO_FLASH     /* We have no parallel FLASH */
80
81
82 /*
83  * SPI Settings
84  */
85 #define CONFIG_BFIN_SPI
86 #define CONFIG_ENV_SPI_MAX_HZ   30000000
87 #define CONFIG_SF_DEFAULT_SPEED 30000000
88 #define CONFIG_SPI_FLASH
89 #define CONFIG_SPI_FLASH_STMICRO
90
91
92 /*
93  * Env Storage Settings
94  */
95 #define CONFIG_ENV_IS_IN_SPI_FLASH
96 #define CONFIG_ENV_OFFSET       0x10000
97 #define CONFIG_ENV_SIZE         0x2000
98 #define CONFIG_ENV_SECT_SIZE    0x10000
99 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
100
101
102 /*
103  * I2C Settings
104  */
105 #define CONFIG_BFIN_TWI_I2C
106 #define CONFIG_HARD_I2C
107
108
109 /*
110  * NAND Settings
111  */
112 #define CONFIG_NAND_PLAT
113 #define CONFIG_SYS_NAND_BASE            0x20000000
114 #define CONFIG_SYS_MAX_NAND_DEVICE      1
115
116 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
117 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
118 #define BFIN_NAND_WRITE(addr, cmd) \
119         do { \
120                 bfin_write8(addr, cmd); \
121                 SSYNC(); \
122         } while (0)
123
124 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
125 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
126 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF9
127
128 /*
129  * Misc Settings
130  */
131 #define CONFIG_BAUDRATE         115200
132 #define CONFIG_RTC_BFIN
133 #define CONFIG_UART_CONSOLE     0
134 #define CONFIG_SYS_PROMPT       "br4>"
135 #define CONFIG_BOOTCOMMAND      "run nandboot"
136 #define CONFIG_BOOTDELAY        2
137 #define CONFIG_LOADADDR         0x2000000
138 #define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
139
140 /*
141  * Pull in common ADI header for remaining command/environment setup
142  */
143 #include <configs/bfin_adi_common.h>
144
145 /*
146  * Overwrite some settings defined in bfin_adi_common.h
147  */
148 #undef NAND_ENV_SETTINGS
149 #define NAND_ENV_SETTINGS \
150         "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
151         "nandboot=" \
152                 "nand read $(loadaddr) 0x0 0x900000;" \
153                 "run nandargs;" \
154                 "bootm" \
155                 "\0"
156
157 #endif