2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /*#define NAND_DEBUG 1 */
28 * SPREADTRUM BIGPHONE board - SoC Configuration
30 #define CONFIG_ARM926EJS /* arm926ejs CPU core */
31 #define CONFIG_SC8800X
32 #define CONFIG_BIGPHONE
34 #define CONFIG_SYS_HZ 1000
35 #define CONFIG_SPRD_TIMER_CLK 1000 /*32768*/
37 #define CONFIG_SYS_HUSH_PARSER
39 #ifdef CONFIG_SYS_HUSH_PARSER
40 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
43 #define CMDLINE_NEED_CONV
45 #define WATCHDOG_LOAD_VALUE 0x4000
46 #define CONFIG_SYS_STACK_SIZE 0x400
48 /*system clock config, it should be in range hardware support */
49 #define CONFIG_SYS_PLL_MHZ 328
50 /* F(AHB)= F(PLL)/AHB_DIV */
51 #define CONFIG_SYS_AHB_DIV 4
52 /* F(ARM) = F(PLL)/ARM_DIV */
53 #define CONFIG_SYS_ARM_DIV 2
54 /* F(EMC) = F(PLL)/EMC_DIV */
55 #define CONFIG_SYS_EMC_DIV 2
58 #ifdef CONFIG_NAND_SPL
59 #define CONFIG_PRELOADER
62 #ifdef CONFIG_NAND_SPL
63 #define CONFIG_SYS_SDRAM_BANK_CNT 2
64 #define CONFIG_SYS_SDRAM_ROW_CNT 2
65 #define CONFIG_SYS_SDRAM_COL_CNT 2
66 #define CONFIG_SYS_SDRAM_DATA_WIDTH 32
67 #define CONFIG_SYS_SDRAM_BURST_LENGTH 3
68 #define CONFIG_SYS_SDRAM_CAS_LATENCY 3
69 #define CONFIG_SYS_SDRAM_EXT_MODE 0xffffffff
70 #define CONFIG_SYS_SDRAM_SIZE_M 64
71 #define CONFIG_SYS_SDRAM_CLK_DELAY 0x2120
73 #define CONFIG_SYS_SDRAM_ROW_REFRESH_MAX 7800
74 #define CONFIG_SYS_SDRAM_ROW_PRECHARGE_MIN 30
75 #define CONFIG_SYS_SDRAM_ROW_CYCLE_MIN 69
76 #define CONFIG_SYS_SDRAM_TRCD_MIN 30
77 #define CONFIG_SYS_SDRAM_TWR_MIN 30
78 #define CONFIG_SYS_SDRAM_TMRD_MIN 2
79 #define CONFIG_SYS_SDRAM_TRFC_MIN 110
80 #define CONFIG_SYS_SDRAM_TXSR_MIN 150
81 #define CONFIG_SYS_SDRAM_TRAS_MIN 90
85 //#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
87 /* NAND BOOT is the only boot method */
88 #define CONFIG_NAND_U_BOOT
89 #define DYNAMIC_CRC_TABLE
90 /* Start copying real U-boot from the second page */
91 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
92 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
93 #ifdef CONFIG_NAND_SPL
94 /* Load U-Boot to this address */
95 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00f00000
96 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
98 #define CONFIG_SYS_SDRAM_BASE 0x00
100 #define CONFIG_SYS_NAND_SPARE_SIZE 64
101 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
102 #define CONFIG_SYS_NAND_PAGE_COUNT 64
103 #define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024)
104 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
106 #define CONFIG_SKIP_LOWLEVEL_INIT
107 #define CONFIG_SKIP_RELOCATE_UBOOT
110 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
111 /* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
112 #define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE
113 /* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
114 //#define CONFIG_SYS_NAND_ECCBYTES 4
115 #define CONFIG_SYS_NAND_ECCBYTES 16
116 /* Number of ECC-blocks per NAND page */
117 #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
118 /* Size of a single OOB region */
119 #define CONFIG_SYS_NAND_OOBSIZE 64
120 /* Number of ECC bytes per page */
121 #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
122 /* ECC byte positions */
123 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
124 48, 49, 50, 51, 52, 53, 54, 55, \
125 56, 57, 58, 59, 60, 61, 62, 63}
127 #define CONFIG_HW_WATCHDOG
129 #define CONFIG_DISPLAY_CPUINFO
131 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
132 #define CONFIG_SETUP_MEMORY_TAGS 1
133 #define CONFIG_INITRD_TAG 1
139 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
140 /* reserved for initial data */
141 #define CONFIG_SYS_GBL_DATA_SIZE 128
143 * Board has 2 32MB banks of DRAM but there is a bug when using
144 * both so only the first is configured
146 #define CONFIG_NR_DRAM_BANKS 1
148 #define PHYS_SDRAM_1 0x00000000
149 #define PHYS_SDRAM_1_SIZE 0x10000000
150 #if (CONFIG_NR_DRAM_BANKS == 2)
151 #define PHYS_SDRAM_2 0x90000000
152 #define PHYS_SDRAM_2_SIZE 0x02000000
155 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
156 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
157 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
162 #define CONFIG_SPRD_UART 1
163 #define CONFIG_SYS_SC8800X_UART1 1
164 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
165 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
166 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
169 * Flash & Environment
171 /* No NOR flash present */
172 #define CONFIG_SYS_MONITOR_LEN ((CONFIG_SYS_NAND_U_BOOT_OFFS)+(CONFIG_SYS_NAND_U_BOOT_SIZE))
173 #define CONFIG_SYS_NO_FLASH 1
174 #define CONFIG_ENV_IS_IN_NAND
175 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
176 #define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */
177 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
180 #define CONFIG_NAND_SPRD
181 #define CONFIG_SPRD_NAND_REGS_BASE (0x60000000)
182 #define CONFIG_SYS_MAX_NAND_DEVICE 1
183 #define CONFIG_SYS_NAND_BASE (0x60000000)
184 //#define CONFIG_JFFS2_NAND
185 #define CONFIG_SPRD_NAND_HWECC
186 #define CONFIG_SYS_NAND_LARGEPAGE
188 #define CONFIG_SYS_64BIT_VSPRINTF
190 #define CONFIG_CMD_MTDPARTS
191 #define CONFIG_MTD_PARTITIONS
192 #define CONFIG_MTD_DEVICE
193 #define CONFIG_CMD_UBI
194 #define CONFIG_RBTREE
196 /* U-Boot general configuration */
197 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
198 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
199 /* Print buffer sz */
200 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
201 sizeof(CONFIG_SYS_PROMPT) + 16)
202 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
203 /* Boot Argument Buffer Size */
204 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
205 #define CONFIG_CMDLINE_EDITING
206 #define CONFIG_SYS_LONGHELP
208 /* support OS choose */
209 #undef CONFIG_BOOTM_NETBSD
210 #undef CONFIG_BOOTM_RTEMS
212 /* U-Boot commands */
213 #include <config_cmd_default.h>
214 #define CONFIG_CMD_NAND
215 #undef CONFIG_CMD_FPGA
216 #undef CONFIG_CMD_LOADS
217 #undef CONFIG_CMD_NET
218 #undef CONFIG_CMD_NFS
219 #undef CONFIG_CMD_SETGETDCR
221 #define CONFIG_ENV_OVERWRITE
223 #define CONFIG_BOOTDELAY 5
225 #define CONFIG_LOADADDR 0x01000000 /* loadaddr env var */
226 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
228 #define xstr(s) str(s)
231 #define MTDIDS_DEFAULT "nand0=sprd-nand"
232 #define MTDPARTS_DEFAULT "mtdparts=sprd-nand:384k@256k(boot),256k(params),6m(kernel),6m(ramdisk),6m(recovery),70m(system),70m(userdata),70m(cache)"
233 #define CONFIG_BOOTARGS "mem=128M console=ttyS1,115200n8 initrd=0x3000000,4194304 init=/init root=/dev/ram0 rw "MTDPARTS_DEFAULT
234 #define CONFIG_BOOTCOMMAND "cboot normal"
235 #define CONFIG_EXTRA_ENV_SETTINGS ""
237 #endif /* __CONFIG_H */