2 * U-boot - Configuration file for BF537 STAMP board
5 #ifndef __CONFIG_BF527_EZKIT_H__
6 #define __CONFIG_BF527_EZKIT_H__
8 #include <asm/config-pre.h>
14 #define CONFIG_BFIN_CPU bf527-0.0
15 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
23 /* CONFIG_CLKIN_HZ is any value in Hz */
24 #define CONFIG_CLKIN_HZ 25000000
25 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
27 #define CONFIG_CLKIN_HALF 0
28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
30 #define CONFIG_PLL_BYPASS 0
31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32 /* Values can range from 0-63 (where 0 means 64) */
33 #define CONFIG_VCO_MULT 21
34 /* CCLK_DIV controls the core clock divider */
35 /* Values can be 1, 2, 4, or 8 ONLY */
36 #define CONFIG_CCLK_DIV 1
37 /* SCLK_DIV controls the system clock divider */
38 /* Values can range from 1-15 */
39 #define CONFIG_SCLK_DIV 4
45 #define CONFIG_MEM_ADD_WDTH 10
46 #define CONFIG_MEM_SIZE 64
48 #define CONFIG_EBIU_SDRRC_VAL 0x03F6
49 #define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
51 #define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
52 #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
53 #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
55 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
56 #define CONFIG_SYS_MALLOC_LEN (640 * 1024)
61 * (can't be used same time as ethernet)
63 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
64 # define CONFIG_BFIN_NFC
65 # define CONFIG_BFIN_NFC_BOOTROM_ECC
67 #ifdef CONFIG_BFIN_NFC
68 #define CONFIG_BFIN_NFC_CTL_VAL 0x0033
69 #define CONFIG_DRIVER_NAND_BFIN
70 #define CONFIG_SYS_NAND_BASE 0 /* not actually used */
71 #define CONFIG_SYS_MAX_NAND_DEVICE 1
78 #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
79 !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
80 #define ADI_CMDS_NETWORK 1
81 #define CONFIG_BFIN_MAC
83 #define CONFIG_NETCONSOLE 1
85 #define CONFIG_HOSTNAME bf527-ezkit
86 /* Uncomment next line to use fixed MAC address */
87 /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
88 #define CONFIG_LIB_RAND
93 #define CONFIG_FLASH_CFI_DRIVER
94 #define CONFIG_SYS_FLASH_BASE 0x20000000
95 #define CONFIG_SYS_FLASH_CFI
96 #define CONFIG_SYS_FLASH_PROTECTION
97 #define CONFIG_SYS_MAX_FLASH_BANKS 1
98 #define CONFIG_SYS_MAX_FLASH_SECT 259
104 #define CONFIG_BFIN_SPI
105 #define CONFIG_ENV_SPI_MAX_HZ 30000000
106 #define CONFIG_SF_DEFAULT_SPEED 30000000
107 #define CONFIG_SPI_FLASH
108 #define CONFIG_SPI_FLASH_STMICRO
112 * Env Storage Settings
114 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
115 #define CONFIG_ENV_IS_IN_SPI_FLASH
116 #define CONFIG_ENV_OFFSET 0x10000
117 #define CONFIG_ENV_SIZE 0x2000
118 #define CONFIG_ENV_SECT_SIZE 0x10000
119 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
120 #elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
121 #define CONFIG_ENV_IS_IN_NAND
122 #define CONFIG_ENV_OFFSET 0x40000
123 #define CONFIG_ENV_SIZE 0x20000
125 #define CONFIG_ENV_IS_IN_FLASH
126 #define CONFIG_ENV_OFFSET 0x4000
127 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
128 #define CONFIG_ENV_SIZE 0x2000
129 #define CONFIG_ENV_SECT_SIZE 0x2000
130 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
137 #define CONFIG_BFIN_TWI_I2C 1
138 #define CONFIG_HARD_I2C 1
144 #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
146 #define CONFIG_MUSB_HCD
147 #define CONFIG_USB_BLACKFIN
148 #define CONFIG_USB_STORAGE
149 #define CONFIG_MUSB_TIMEOUT 100000
152 /* Don't waste time transferring a logo over the UART */
153 #if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
154 /*# define CONFIG_VIDEO*/
161 #ifdef CONFIG_BF527_EZKIT_REV_2_1
162 # define CONFIG_LQ035Q1_SPI_BUS 0
163 # define CONFIG_LQ035Q1_SPI_CS 7
164 # define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
166 # define CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
169 #ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
170 # define EASYLOGO_HEADER <asm/bfin_logo_rgb565_230x230_lzma.h>
172 # define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h>
174 #endif /* CONFIG_VIDEO */
179 #define CONFIG_MISC_INIT_R
180 #define CONFIG_RTC_BFIN
181 #define CONFIG_UART_CONSOLE 1
182 #define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
185 * Pull in common ADI header for remaining command/environment setup
187 #include <configs/bfin_adi_common.h>