2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 /************************************************************************
9 * bamboo.h - configuration for BAMBOO board
10 ***********************************************************************/
14 /*-----------------------------------------------------------------------
15 * High Level Configuration Options
16 *----------------------------------------------------------------------*/
17 #define CONFIG_BAMBOO 1 /* Board is BAMBOO */
18 #define CONFIG_440EP 1 /* Specific PPC440EP support */
19 #define CONFIG_440 1 /* ... PPC440 family */
20 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
22 #ifndef CONFIG_SYS_TEXT_BASE
23 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000
27 * Include common defines/options for all AMCC eval boards
29 #define CONFIG_HOSTNAME bamboo
30 #include "amcc-common.h"
32 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
35 * Please note that, if NAND support is enabled, the 2nd ethernet port
36 * can't be used because of pin multiplexing. So, if you want to use the
37 * 2nd ethernet port you have to "undef" the following define.
39 #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
41 /*-----------------------------------------------------------------------
42 * Base addresses -- Note these are effective addresses where the
43 * actual resources get mapped (not physical addresses)
44 *----------------------------------------------------------------------*/
45 #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
46 #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
47 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
48 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
49 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
51 /*Don't change either of these*/
52 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
53 /*Don't change either of these*/
55 #define CONFIG_SYS_USB_DEVICE 0x50000000
56 #define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
57 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
58 #define CONFIG_SYS_NAND_ADDR 0x90000000
59 #define CONFIG_SYS_NAND2_ADDR 0x94000000
61 /*-----------------------------------------------------------------------
62 * Initial RAM & stack pointer (placed in SDRAM)
63 *----------------------------------------------------------------------*/
64 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
65 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
66 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
67 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
68 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
70 /*-----------------------------------------------------------------------
72 *----------------------------------------------------------------------*/
73 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
74 #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
76 /*-----------------------------------------------------------------------
79 * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
80 * The DS1558 code assumes this condition
82 *----------------------------------------------------------------------*/
83 #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
84 #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
86 /*-----------------------------------------------------------------------
88 *----------------------------------------------------------------------*/
89 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
91 /*-----------------------------------------------------------------------
93 *----------------------------------------------------------------------*/
94 #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
95 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
97 #undef CONFIG_SYS_FLASH_CHECKSUM
98 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
99 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
101 #define CONFIG_SYS_FLASH_ADDR0 0x555
102 #define CONFIG_SYS_FLASH_ADDR1 0x2aa
103 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
105 #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
106 #define CONFIG_SYS_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
108 #ifdef CONFIG_ENV_IS_IN_FLASH
109 #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
110 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
111 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
113 /* Address and size of Redundant Environment Sector */
114 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
115 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
116 #endif /* CONFIG_ENV_IS_IN_FLASH */
118 /*-----------------------------------------------------------------------
120 *----------------------------------------------------------------------*/
121 #define CONFIG_SYS_MAX_NAND_DEVICE 2
122 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
123 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
124 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
125 #define CONFIG_SYS_NAND_CS 1
127 /*-----------------------------------------------------------------------
129 *----------------------------------------------------------------------------- */
130 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
131 #undef CONFIG_DDR_ECC /* don't use ECC */
132 #define CONFIG_SYS_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
133 #define SPD_EEPROM_ADDRESS {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
134 #define CONFIG_SYS_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
135 #define CONFIG_PROG_SDRAM_TLB
137 /*-----------------------------------------------------------------------
139 *----------------------------------------------------------------------*/
140 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
142 #define CONFIG_SYS_I2C_MULTI_EEPROMS
143 #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
145 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
146 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
148 #ifdef CONFIG_ENV_IS_IN_EEPROM
149 #define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
150 #define CONFIG_ENV_OFFSET 0x0
151 #endif /* CONFIG_ENV_IS_IN_EEPROM */
154 * Default environment variables
156 #define CONFIG_EXTRA_ENV_SETTINGS \
157 CONFIG_AMCC_DEF_ENV \
158 CONFIG_AMCC_DEF_ENV_POWERPC \
159 CONFIG_AMCC_DEF_ENV_PPC_OLD \
160 CONFIG_AMCC_DEF_ENV_NOR_UPD \
161 "kernel_addr=fff00000\0" \
162 "ramdisk_addr=fff10000\0" \
165 #define CONFIG_HAS_ETH0
166 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
167 #define CONFIG_PHY1_ADDR 1
169 #ifndef CONFIG_BAMBOO_NAND
170 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
171 #endif /* CONFIG_BAMBOO_NAND */
175 #define CONFIG_USB_OHCI
176 #define CONFIG_USB_STORAGE
178 /*Comment this out to enable USB 1.1 device*/
179 #define USB_2_0_DEVICE
180 #endif /*CONFIG_440EP*/
183 * Commands additional to the ones defined in amcc-common.h
185 #define CONFIG_CMD_DATE
186 #define CONFIG_CMD_EXT2
187 #define CONFIG_CMD_FAT
188 #define CONFIG_CMD_PCI
189 #define CONFIG_CMD_SDRAM
190 #define CONFIG_CMD_SNTP
191 #define CONFIG_CMD_USB
193 #ifdef CONFIG_BAMBOO_NAND
194 #define CONFIG_CMD_NAND
197 #define CONFIG_SUPPORT_VFAT
200 #define CONFIG_MAC_PARTITION
201 #define CONFIG_DOS_PARTITION
202 #define CONFIG_ISO_PARTITION
204 /*-----------------------------------------------------------------------
206 *-----------------------------------------------------------------------
209 #define CONFIG_PCI /* include pci support */
210 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
211 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
212 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
213 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
215 /* Board-specific PCI */
216 #define CONFIG_SYS_PCI_TARGET_INIT
217 #define CONFIG_SYS_PCI_MASTER_INIT
219 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
220 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
222 #endif /* __CONFIG_H */