include/configs/axs101.h

   1 /*
   2  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _CONFIG_AXS101_H_
   8 #define _CONFIG_AXS101_H_
   9
  10 /*
  11  *  CPU configuration
  12  */
  13 #define CONFIG_SYS_TIMER_RATE           CONFIG_SYS_CLK_FREQ
  14
  15 /*
  16  * Board configuration
  17  */
  18 #define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is in RAM already */
  19
  20 #define CONFIG_ARCH_EARLY_INIT_R
  21
  22 #define ARC_FPGA_PERIPHERAL_BASE        0xE0000000
  23 #define ARC_APB_PERIPHERAL_BASE         0xF0000000
  24 #define ARC_DWMMC_BASE                  (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
  25 #define ARC_DWGMAC_BASE                 (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
  26
  27 /*
  28  * Memory configuration
  29  */
  30 #define CONFIG_SYS_TEXT_BASE            0x81000000
  31 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  32
  33 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  34 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  35 #define CONFIG_SYS_SDRAM_SIZE           0x20000000      /* 512 Mb */
  36
  37 #define CONFIG_SYS_INIT_SP_ADDR         \
  38         (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
  39
  40 #define CONFIG_SYS_MALLOC_LEN           0x200000        /* 2 MB */
  41 #define CONFIG_SYS_BOOTM_LEN            0x2000000       /* 32 MB */
  42 #define CONFIG_SYS_LOAD_ADDR            0x82000000
  43
  44 /*
  45  * NAND Flash configuration
  46  */
  47 #define CONFIG_SYS_NO_FLASH
  48 #define CONFIG_SYS_NAND_BASE            (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
  49 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  50
  51 /*
  52  * UART configuration
  53  *
  54  * CONFIG_CONS_INDEX = 1 - Debug UART
  55  * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
  56  */
  57 #define CONFIG_CONS_INDEX               4
  58 #define CONFIG_SYS_NS16550
  59 #define CONFIG_SYS_NS16550_SERIAL
  60 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  61 #if (CONFIG_CONS_INDEX == 1)
  62         /* Debug UART */
  63 #       define CONFIG_SYS_NS16550_CLK           33333000
  64 #else
  65         /* FPGA UARTs use different clock */
  66 #       define CONFIG_SYS_NS16550_CLK           33333333
  67 #endif
  68 #define CONFIG_SYS_NS16550_COM1         (ARC_APB_PERIPHERAL_BASE + 0x5000)
  69 #define CONFIG_SYS_NS16550_COM2         (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
  70 #define CONFIG_SYS_NS16550_COM3         (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
  71 #define CONFIG_SYS_NS16550_COM4         (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
  72 #define CONFIG_SYS_NS16550_MEM32
  73
  74 #define CONFIG_BAUDRATE                 115200
  75 /*
  76  * I2C configuration
  77  */
  78 #define CONFIG_SYS_I2C
  79 #define CONFIG_SYS_I2C_DW
  80 #define CONFIG_I2C_ENV_EEPROM_BUS       2
  81 #define CONFIG_SYS_I2C_SPEED            100000
  82 #define CONFIG_SYS_I2C_SPEED1           100000
  83 #define CONFIG_SYS_I2C_SPEED2           100000
  84 #define CONFIG_SYS_I2C_SLAVE            0
  85 #define CONFIG_SYS_I2C_SLAVE1           0
  86 #define CONFIG_SYS_I2C_SLAVE2           0
  87 #define CONFIG_SYS_I2C_BASE             0xE001D000
  88 #define CONFIG_SYS_I2C_BASE1            0xE001E000
  89 #define CONFIG_SYS_I2C_BASE2            0xE001F000
  90 #define CONFIG_SYS_I2C_BUS_MAX          3
  91 #define IC_CLK                          50
  92
  93 /*
  94  * EEPROM configuration
  95  */
  96 #define CONFIG_SYS_I2C_MULTI_EEPROMS
  97 #define CONFIG_SYS_I2C_EEPROM_ADDR              (0xA8 >> 1)
  98 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
  99 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     1
 100 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 101 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   64
 102
 103 /*
 104  * SD/MMC configuration
 105  */
 106 #define CONFIG_MMC
 107 #define CONFIG_GENERIC_MMC
 108 #define CONFIG_DWMMC
 109 #define CONFIG_DOS_PARTITION
 110
 111 /*
 112  * Ethernet PHY configuration
 113  */
 114 #define CONFIG_PHYLIB
 115 #define CONFIG_MII
 116 #define CONFIG_PHY_GIGE
 117
 118 /*
 119  * Ethernet configuration
 120  */
 121 #define CONFIG_DESIGNWARE_ETH
 122 #define CONFIG_DW_AUTONEG
 123 #define CONFIG_NET_MULTI
 124
 125 /*
 126  * Command line configuration
 127  */
 128 #include <config_cmd_default.h>
 129
 130 #define CONFIG_CMD_DHCP
 131 #define CONFIG_CMD_EEPROM
 132 #define CONFIG_CMD_ELF
 133 #define CONFIG_CMD_FAT
 134 #define CONFIG_CMD_I2C
 135 #define CONFIG_CMD_MMC
 136 #define CONFIG_CMD_NAND
 137 #define CONFIG_CMD_PING
 138 #define CONFIG_CMD_RARP
 139
 140 #define CONFIG_OF_LIBFDT
 141
 142 #define CONFIG_AUTO_COMPLETE
 143 #define CONFIG_SYS_MAXARGS              16
 144
 145 /*
 146  * Environment settings
 147  */
 148 #define CONFIG_ENV_IS_IN_EEPROM
 149 #define CONFIG_ENV_SIZE                 0x00200         /* 512 bytes */
 150 #define CONFIG_ENV_OFFSET               0
 151
 152 /*
 153  * Environment configuration
 154  */
 155 #define CONFIG_BOOTDELAY                3
 156 #define CONFIG_BOOTFILE                 "uImage"
 157 #define CONFIG_BOOTARGS                 "console=ttyS3,115200n8"
 158 #define CONFIG_LOADADDR                 CONFIG_SYS_LOAD_ADDR
 159
 160 /*
 161  * Console configuration
 162  */
 163 #define CONFIG_SYS_LONGHELP
 164 #define CONFIG_SYS_PROMPT               "AXS# "
 165 #define CONFIG_SYS_CBSIZE               256
 166 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 167 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 168                                                 sizeof(CONFIG_SYS_PROMPT) + 16)
 169
 170 /*
 171  * Misc utility configuration
 172  */
 173 #define CONFIG_BOUNCE_BUFFER
 174
 175 #endif /* _CONFIG_AXS101_H_ */