1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
11 #define CONFIG_SPL_MAX_SIZE 0x00100000
12 #define CONFIG_SPL_BSS_START_ADDR 0x04000000
13 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
16 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x00200000
18 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80010000
21 #ifdef CONFIG_SPL_MMC_SUPPORT
22 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
23 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
28 * CPU and Board Configuration Options
32 * Miscellaneous configurable options
34 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
39 #define CONFIG_SYS_PBSIZE \
40 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
43 * max number of command args
45 #define CONFIG_SYS_MAXARGS 16
48 * Boot Argument Buffer Size
50 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
53 * Size of malloc() pool
54 * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
56 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
58 /* DT blob (fdt) address */
59 #define CONFIG_SYS_FDT_BASE 0x800f0000
64 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
65 #define PHYS_SDRAM_1 \
66 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
67 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
68 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
69 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
72 * Serial console configuration
74 #define CONFIG_SYS_NS16550_SERIAL
75 #ifndef CONFIG_DM_SERIAL
76 #define CONFIG_SYS_NS16550_REG_SIZE -4
78 #define CONFIG_SYS_NS16550_CLK 19660800
80 /* Init Stack Pointer */
81 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
82 GENERATED_GBL_DATA_SIZE)
85 * Load address and memory test area should agree with
86 * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself.
88 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */
91 * memtest works on 512 MB in DRAM
95 * FLASH and environment organization
98 /* use CFI framework */
100 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
101 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
104 #ifdef CONFIG_CFI_FLASH
105 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
106 #endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
107 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */
108 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
109 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
110 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
112 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
115 /* max number of memory banks */
117 * There are 4 banks supported for this Controller,
118 * but we have only 1 bank connected to flash on board
120 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
121 #define CONFIG_SYS_MAX_FLASH_BANKS 1
123 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
125 /* max number of sectors on one chip */
126 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
127 #define CONFIG_SYS_MAX_FLASH_SECT 512
134 * For booting Linux, the board info and command line data
135 * have to be in the first 16 MB of memory, since this is
136 * the maximum mapped by the Linux kernel during initialization.
139 /* Initial Memory map for Linux*/
140 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
141 /* Increase max gunzip size */
142 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
144 /* When we use RAM as ENV */
146 /* Enable distro boot */
147 #define BOOT_TARGET_DEVICES(func) \
150 #include <config_distro_bootcmd.h>
152 #define CONFIG_EXTRA_ENV_SETTINGS \
153 "kernel_addr_r=0x00080000\0" \
154 "pxefile_addr_r=0x01f00000\0" \
155 "scriptaddr=0x01f00000\0" \
156 "fdt_addr_r=0x02000000\0" \
157 "ramdisk_addr_r=0x02800000\0" \
160 #endif /* __CONFIG_H */