1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
11 #define CONFIG_SPL_MAX_SIZE 0x00100000
12 #define CONFIG_SPL_BSS_START_ADDR 0x04000000
13 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
15 #ifdef CONFIG_SPL_MMC_SUPPORT
16 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
20 #define RISCV_MMODE_TIMERBASE 0xe6000000
21 #define RISCV_MMODE_TIMER_FREQ 60000000
23 #define RISCV_SMODE_TIMER_FREQ 60000000
26 * CPU and Board Configuration Options
30 * Miscellaneous configurable options
32 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
37 #define CONFIG_SYS_PBSIZE \
38 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
41 * max number of command args
43 #define CONFIG_SYS_MAXARGS 16
46 * Boot Argument Buffer Size
48 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
51 * Size of malloc() pool
52 * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
54 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
56 /* DT blob (fdt) address */
57 #define CONFIG_SYS_FDT_BASE 0x800f0000
62 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
63 #define PHYS_SDRAM_1 \
64 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
65 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
66 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
67 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
70 * Serial console configuration
72 #define CONFIG_SYS_NS16550_SERIAL
73 #ifndef CONFIG_DM_SERIAL
74 #define CONFIG_SYS_NS16550_REG_SIZE -4
76 #define CONFIG_SYS_NS16550_CLK 19660800
78 /* Init Stack Pointer */
79 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
80 GENERATED_GBL_DATA_SIZE)
82 /* use CFI framework */
84 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
85 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
88 #ifdef CONFIG_CFI_FLASH
89 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
90 #endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
91 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */
92 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
93 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
94 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
96 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
97 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
99 /* max number of memory banks */
101 * There are 4 banks supported for this Controller,
102 * but we have only 1 bank connected to flash on board
104 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
105 #define CONFIG_SYS_MAX_FLASH_BANKS 1
107 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
109 /* max number of sectors on one chip */
110 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
111 #define CONFIG_SYS_MAX_FLASH_SECT 512
118 * For booting Linux, the board info and command line data
119 * have to be in the first 16 MB of memory, since this is
120 * the maximum mapped by the Linux kernel during initialization.
123 /* Initial Memory map for Linux*/
124 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
125 /* Increase max gunzip size */
126 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
128 /* When we use RAM as ENV */
130 /* Enable distro boot */
131 #define BOOT_TARGET_DEVICES(func) \
134 #include <config_distro_bootcmd.h>
136 #define CONFIG_EXTRA_ENV_SETTINGS \
137 "kernel_addr_r=0x00080000\0" \
138 "pxefile_addr_r=0x01f00000\0" \
139 "scriptaddr=0x01f00000\0" \
140 "fdt_addr_r=0x02000000\0" \
141 "ramdisk_addr_r=0x02800000\0" \
144 #endif /* __CONFIG_H */