include/configs/atstk1002.h

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * Configuration settings for the ATSTK1002 CPU daughterboard
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 #define CONFIG_AVR32                    1
  28 #define CONFIG_AT32AP                   1
  29 #define CONFIG_AT32AP7000               1
  30 #define CONFIG_ATSTK1002                1
  31 #define CONFIG_ATSTK1000                1
  32
  33 #define CONFIG_ATSTK1000_EXT_FLASH      1
  34
  35 /*
  36  * Timer clock frequency. We're using the CPU-internal COUNT register
  37  * for this, so this is equivalent to the CPU core clock frequency
  38  */
  39 #define CFG_HZ                          1000
  40
  41 /*
  42  * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
  43  * frequency and the peripherals to run at 1/4 the PLL frequency.
  44  */
  45 #define CONFIG_PLL                      1
  46 #define CFG_POWER_MANAGER               1
  47 #define CFG_OSC0_HZ                     20000000
  48 #define CFG_PLL0_DIV                    1
  49 #define CFG_PLL0_MUL                    7
  50 #define CFG_PLL0_SUPPRESS_CYCLES        16
  51 #define CFG_CLKDIV_CPU                  0
  52 #define CFG_CLKDIV_HSB                  1
  53 #define CFG_CLKDIV_PBA                  2
  54 #define CFG_CLKDIV_PBB                  1
  55
  56 /*
  57  * The PLLOPT register controls the PLL like this:
  58  *   icp = PLLOPT<2>
  59  *   ivco = PLLOPT<1:0>
  60  *
  61  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  62  */
  63 #define CFG_PLL0_OPT                    0x04
  64
  65 #define CFG_USART1                      1
  66
  67 #define CFG_CONSOLE_UART_DEV            DEVICE_USART1
  68
  69 /* User serviceable stuff */
  70 #define CONFIG_CMDLINE_TAG              1
  71 #define CONFIG_SETUP_MEMORY_TAGS        1
  72 #define CONFIG_INITRD_TAG               1
  73
  74 #define CONFIG_STACKSIZE                (2048)
  75
  76 #define CONFIG_BAUDRATE                 115200
  77 #define CONFIG_BOOTARGS                                                 \
  78         "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k"
  79
  80 #define CONFIG_COMMANDS                 (CFG_CMD_BDI                    \
  81                                          | CFG_CMD_LOADS                \
  82                                          | CFG_CMD_LOADB                \
  83                                          /* | CFG_CMD_IMI */            \
  84                                          /* | CFG_CMD_CACHE */          \
  85                                          | CFG_CMD_FLASH                \
  86                                          | CFG_CMD_MEMORY               \
  87                                          /* | CFG_CMD_NET */            \
  88                                          | CFG_CMD_ENV                  \
  89                                          /* | CFG_CMD_IRQ */            \
  90                                          | CFG_CMD_BOOTD                \
  91                                          | CFG_CMD_CONSOLE              \
  92                                          /* | CFG_CMD_EEPROM */         \
  93                                          | CFG_CMD_ASKENV               \
  94                                          | CFG_CMD_RUN                  \
  95                                          | CFG_CMD_ECHO                 \
  96                                          /* | CFG_CMD_I2C */            \
  97                                          | CFG_CMD_REGINFO              \
  98                                          /* | CFG_CMD_DATE */           \
  99                                          /* | CFG_CMD_DHCP */           \
 100                                          /* | CFG_CMD_AUTOSCRIPT */     \
 101                                          /* | CFG_CMD_MII */            \
 102                                          | CFG_CMD_MISC                 \
 103                                          /* | CFG_CMD_SDRAM */          \
 104                                          /* | CFG_CMD_DIAG */           \
 105                                          /* | CFG_CMD_HWFLOW */         \
 106                                          /* | CFG_CMD_SAVES */          \
 107                                          /* | CFG_CMD_SPI */            \
 108                                          /* | CFG_CMD_PING */           \
 109                                          /* | CFG_CMD_MMC */            \
 110                                          /* | CFG_CMD_FAT */            \
 111                                          /* | CFG_CMD_IMLS */           \
 112                                          /* | CFG_CMD_ITEST */          \
 113                                          /* | CFG_CMD_EXT2 */           \
 114                 )
 115
 116 #include <cmd_confdefs.h>
 117
 118 #define CONFIG_ATMEL_USART              1
 119 #define CONFIG_PIO2                     1
 120 #define CFG_NR_PIOS                     5
 121 #define CFG_HSDRAMC                     1
 122
 123 #define CFG_DCACHE_LINESZ               32
 124 #define CFG_ICACHE_LINESZ               32
 125
 126 #define CONFIG_NR_DRAM_BANKS            1
 127
 128 /* External flash on STK1000 */
 129 #if 0
 130 #define CFG_FLASH_CFI                   1
 131 #define CFG_FLASH_CFI_DRIVER            1
 132 #endif
 133
 134 #define CFG_FLASH_BASE                  0x00000000
 135 #define CFG_FLASH_SIZE                  0x800000
 136 #define CFG_MAX_FLASH_BANKS             1
 137 #define CFG_MAX_FLASH_SECT              135
 138
 139 #define CFG_MONITOR_BASE                CFG_FLASH_BASE
 140
 141 #define CFG_INTRAM_BASE                 0x24000000
 142 #define CFG_INTRAM_SIZE                 0x8000
 143
 144 #define CFG_SDRAM_BASE                  0x10000000
 145
 146 #define CFG_ENV_IS_IN_FLASH             1
 147 #define CFG_ENV_SIZE                    65536
 148 #define CFG_ENV_ADDR                    (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
 149
 150 #define CFG_INIT_SP_ADDR                (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
 151
 152 #define CFG_MALLOC_LEN                  (256*1024)
 153 #define CFG_MALLOC_END                                                  \
 154         ({                                                              \
 155                 DECLARE_GLOBAL_DATA_PTR;                                \
 156                 CFG_SDRAM_BASE + gd->sdram_size;                        \
 157         })
 158 #define CFG_MALLOC_START                (CFG_MALLOC_END - CFG_MALLOC_LEN)
 159
 160 #define CFG_DMA_ALLOC_LEN               (16384)
 161 #define CFG_DMA_ALLOC_END               (CFG_MALLOC_START)
 162 #define CFG_DMA_ALLOC_START             (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
 163 /* Allow 2MB for the kernel run-time image */
 164 #define CFG_LOAD_ADDR                   (CFG_SDRAM_BASE + 0x00200000)
 165 #define CFG_BOOTPARAMS_LEN              (16 * 1024)
 166
 167 /* Other configuration settings that shouldn't have to change all that often */
 168 #define CFG_PROMPT                      "Uboot> "
 169 #define CFG_CBSIZE                      256
 170 #define CFG_MAXARGS                     8
 171 #define CFG_PBSIZE                      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 172 #define CFG_LONGHELP                    1
 173
 174 #define CFG_MEMTEST_START                                               \
 175         ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
 176 #define CFG_MEMTEST_END                                                 \
 177         ({                                                              \
 178                 DECLARE_GLOBAL_DATA_PTR;                                \
 179                 gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;     \
 180         })
 181 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 182
 183 #endif /* __CONFIG_H */