3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_ATC 1 /* ...on a ATC board */
21 #define CONFIG_CPM2 1 /* Has a CPM2 */
23 #define CONFIG_SYS_TEXT_BASE 0xFF000000
26 * select serial console configuration
28 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
29 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
32 * if CONFIG_CONS_NONE is defined, then the serial console routines must
33 * defined elsewhere (for example, on the cogent platform, there are serial
34 * ports on the motherboard which are used for the serial console - see
35 * cogent/cma101/serial.[ch]).
37 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
38 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
39 #undef CONFIG_CONS_NONE /* define if console on something else*/
40 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
42 #define CONFIG_BAUDRATE 115200
45 * select ethernet configuration
47 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
48 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
51 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
52 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
54 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
55 #undef CONFIG_ETHER_NONE /* define if ether on something else */
56 #define CONFIG_ETHER_ON_FCC
58 #define CONFIG_ETHER_ON_FCC2
63 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
64 * - Enable Full Duplex in FSMR
66 # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
67 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
68 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
69 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
71 #define CONFIG_ETHER_ON_FCC3
76 * - RAM for BD/Buffers is on the local Bus (see 28-13)
77 * - Enable Half Duplex in FSMR
79 # define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
80 # define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
82 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
83 #define CONFIG_8260_CLKIN 64000000 /* in Hz */
85 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
87 #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
89 #define CONFIG_PREBOOT \
91 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
94 #undef CONFIG_BOOTARGS
95 #define CONFIG_BOOTCOMMAND \
97 "setenv bootargs root=/dev/nfs rw " \
98 "nfsroot=${serverip}:${rootpath} " \
99 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
102 /*-----------------------------------------------------------------------
103 * Miscellaneous configuration options
106 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
107 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
113 #define CONFIG_BOOTP_SUBNETMASK
114 #define CONFIG_BOOTP_GATEWAY
115 #define CONFIG_BOOTP_HOSTNAME
116 #define CONFIG_BOOTP_BOOTPATH
117 #define CONFIG_BOOTP_BOOTFILESIZE
121 * Command line configuration.
123 #include <config_cmd_default.h>
125 #define CONFIG_CMD_EEPROM
126 #define CONFIG_CMD_PCI
127 #define CONFIG_CMD_PCMCIA
128 #define CONFIG_CMD_DATE
129 #define CONFIG_CMD_IDE
132 #define CONFIG_DOS_PARTITION
135 * Miscellaneous configurable options
137 #define CONFIG_SYS_LONGHELP /* undef to save memory */
138 #if defined(CONFIG_CMD_KGDB)
139 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
141 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
143 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
144 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
145 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
147 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
148 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
150 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
152 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
154 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
156 #define CONFIG_SYS_ALLOC_DPRAM
158 #undef CONFIG_WATCHDOG /* watchdog disabled */
162 #define CONFIG_RTC_DS12887
164 #define RTC_BASE_ADDR 0xF5000000
165 #define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
166 #define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
168 #define CONFIG_MISC_INIT_R
171 * For booting Linux, the board info and command line data
172 * have to be in the first 8 MB of memory, since this is
173 * the maximum mapped by the Linux kernel during initialization.
175 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
177 /*-----------------------------------------------------------------------
178 * Flash configuration
181 #define CONFIG_SYS_FLASH_BASE 0xFF000000
182 #define CONFIG_SYS_FLASH_SIZE 0x00800000
184 /*-----------------------------------------------------------------------
187 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
188 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
190 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
191 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
193 #define CONFIG_FLASH_16BIT
195 /*-----------------------------------------------------------------------
196 * Hard Reset Configuration Words
198 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
199 * defines for the various registers affected by the HRCW e.g. changing
200 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
202 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
206 /* no slaves so just fill with zeros */
207 #define CONFIG_SYS_HRCW_SLAVE1 0
208 #define CONFIG_SYS_HRCW_SLAVE2 0
209 #define CONFIG_SYS_HRCW_SLAVE3 0
210 #define CONFIG_SYS_HRCW_SLAVE4 0
211 #define CONFIG_SYS_HRCW_SLAVE5 0
212 #define CONFIG_SYS_HRCW_SLAVE6 0
213 #define CONFIG_SYS_HRCW_SLAVE7 0
215 /*-----------------------------------------------------------------------
216 * Internal Memory Mapped Register
218 #define CONFIG_SYS_IMMR 0xF0000000
220 /*-----------------------------------------------------------------------
221 * Definitions for initial stack pointer and data area (in DPRAM)
223 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
224 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
225 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
226 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
228 /*-----------------------------------------------------------------------
229 * Start addresses for the final memory configuration
230 * (Set up by the startup code)
231 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
233 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
235 #define CONFIG_SYS_SDRAM_BASE 0x00000000
236 #define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
237 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
238 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
239 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
241 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
242 # define CONFIG_SYS_RAMBOOT
246 #define CONFIG_PCI_INDIRECT_BRIDGE
247 #define CONFIG_PCI_PNP
248 #define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
251 /* environment is in Flash */
252 #define CONFIG_ENV_IS_IN_FLASH 1
253 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000)
254 # define CONFIG_ENV_SIZE 0x10000
255 # define CONFIG_ENV_SECT_SIZE 0x10000
257 #define CONFIG_ENV_IS_IN_EEPROM 1
258 #define CONFIG_ENV_OFFSET 0
259 #define CONFIG_ENV_SIZE 2048
260 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
263 /*-----------------------------------------------------------------------
264 * Cache Configuration
266 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
267 #if defined(CONFIG_CMD_KGDB)
268 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
271 /*-----------------------------------------------------------------------
272 * HIDx - Hardware Implementation-dependent Registers 2-11
273 *-----------------------------------------------------------------------
274 * HID0 also contains cache control - initially enable both caches and
275 * invalidate contents, then the final state leaves only the instruction
276 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
277 * but Soft reset does not.
279 * HID1 has only read-only information - nothing to set.
281 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
282 HID0_DCI|HID0_IFEM|HID0_ABE)
283 #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
284 #define CONFIG_SYS_HID2 0
286 /*-----------------------------------------------------------------------
287 * RMR - Reset Mode Register 5-5
288 *-----------------------------------------------------------------------
289 * turn on Checkstop Reset Enable
291 #define CONFIG_SYS_RMR RMR_CSRE
293 /*-----------------------------------------------------------------------
294 * BCR - Bus Configuration 4-25
295 *-----------------------------------------------------------------------
297 #define BCR_APD01 0x10000000
298 #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
300 /*-----------------------------------------------------------------------
301 * SIUMCR - SIU Module Configuration 4-31
302 *-----------------------------------------------------------------------
304 #define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\
305 SIUMCR_CS10PC00|SIUMCR_BCTLC10)
307 /*-----------------------------------------------------------------------
308 * SYPCR - System Protection Control 4-35
309 * SYPCR can only be written once after reset!
310 *-----------------------------------------------------------------------
311 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
313 #if defined(CONFIG_WATCHDOG)
314 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
315 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
317 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
318 SYPCR_SWRI|SYPCR_SWP)
319 #endif /* CONFIG_WATCHDOG */
321 /*-----------------------------------------------------------------------
322 * TMCNTSC - Time Counter Status and Control 4-40
323 *-----------------------------------------------------------------------
324 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
325 * and enable Time Counter
327 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
329 /*-----------------------------------------------------------------------
330 * PISCR - Periodic Interrupt Status and Control 4-42
331 *-----------------------------------------------------------------------
332 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
335 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
337 /*-----------------------------------------------------------------------
338 * SCCR - System Clock Control 9-8
339 *-----------------------------------------------------------------------
340 * Ensure DFBRG is Divide by 16
342 #define CONFIG_SYS_SCCR SCCR_DFBRG01
344 /*-----------------------------------------------------------------------
345 * RCCR - RISC Controller Configuration 13-7
346 *-----------------------------------------------------------------------
348 #define CONFIG_SYS_RCCR 0
350 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
351 /*-----------------------------------------------------------------------
352 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
353 *-----------------------------------------------------------------------
355 #define CONFIG_SYS_MPTPR 0x1F00
357 /*-----------------------------------------------------------------------
358 * PSRT - Refresh Timer Register 10-16
359 *-----------------------------------------------------------------------
361 #define CONFIG_SYS_PSRT 0x0f
363 /*-----------------------------------------------------------------------
364 * PSRT - SDRAM Mode Register 10-10
365 *-----------------------------------------------------------------------
368 /* SDRAM initialization values for 8-column chips
370 #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
372 ORxS_ROWST_PBI1_A7 |\
375 #define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
376 PSDMR_SDAM_A15_IS_A5 |\
377 PSDMR_BSMA_A15_A17 |\
378 PSDMR_SDA10_PBI1_A7 |\
386 /* SDRAM initialization values for 9-column chips
388 #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
390 ORxS_ROWST_PBI1_A6 |\
393 #define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
394 PSDMR_SDAM_A16_IS_A5 |\
395 PSDMR_BSMA_A15_A17 |\
396 PSDMR_SDA10_PBI1_A6 |\
405 * Init Memory Controller:
407 * Bank Bus Machine PortSz Device
408 * ---- --- ------- ------ ------
409 * 0 60x GPCM 8 bit Boot ROM
410 * 1 60x GPCM 64 bit FLASH
411 * 2 60x SDRAM 64 bit SDRAM
415 #define CONFIG_SYS_MRS_OFFS 0x00000000
419 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
424 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
431 /* Bank 2 - 60x bus SDRAM
433 #ifndef CONFIG_SYS_RAMBOOT
434 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
439 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
441 #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
442 #endif /* CONFIG_SYS_RAMBOOT */
444 #define CONFIG_SYS_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\
449 #define CONFIG_SYS_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI)
451 /*-----------------------------------------------------------------------
453 *-----------------------------------------------------------------------
456 #define CONFIG_I82365
458 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x81000000
459 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
461 /*-----------------------------------------------------------------------
462 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
463 *-----------------------------------------------------------------------
466 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
467 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
469 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
470 #undef CONFIG_IDE_LED /* LED for ide not supported */
471 #undef CONFIG_IDE_RESET /* reset for ide not supported */
473 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
474 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
476 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
478 #define CONFIG_SYS_ATA_BASE_ADDR 0xa0000000
480 /* Offset for data I/O */
481 #define CONFIG_SYS_ATA_DATA_OFFSET 0x100
483 /* Offset for normal register accesses */
484 #define CONFIG_SYS_ATA_REG_OFFSET 0x100
486 /* Offset for alternate registers */
487 #define CONFIG_SYS_ATA_ALT_OFFSET 0x108
489 #endif /* __CONFIG_H */