3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
21 #define CONFIG_ATC 1 /* ...on a ATC board */
22 #define CONFIG_CPM2 1 /* Has a CPM2 */
24 #define CONFIG_SYS_TEXT_BASE 0xFF000000
27 * select serial console configuration
29 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
30 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
33 * if CONFIG_CONS_NONE is defined, then the serial console routines must
34 * defined elsewhere (for example, on the cogent platform, there are serial
35 * ports on the motherboard which are used for the serial console - see
36 * cogent/cma101/serial.[ch]).
38 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
39 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
40 #undef CONFIG_CONS_NONE /* define if console on something else*/
41 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
43 #define CONFIG_BAUDRATE 115200
46 * select ethernet configuration
48 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
49 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
52 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
53 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
55 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
56 #undef CONFIG_ETHER_NONE /* define if ether on something else */
57 #define CONFIG_ETHER_ON_FCC
59 #define CONFIG_ETHER_ON_FCC2
64 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
65 * - Enable Full Duplex in FSMR
67 # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
68 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
69 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
70 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
72 #define CONFIG_ETHER_ON_FCC3
77 * - RAM for BD/Buffers is on the local Bus (see 28-13)
78 * - Enable Half Duplex in FSMR
80 # define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
81 # define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
83 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
84 #define CONFIG_8260_CLKIN 64000000 /* in Hz */
86 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
88 #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
90 #define CONFIG_PREBOOT \
92 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
95 #undef CONFIG_BOOTARGS
96 #define CONFIG_BOOTCOMMAND \
98 "setenv bootargs root=/dev/nfs rw " \
99 "nfsroot=${serverip}:${rootpath} " \
100 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
103 /*-----------------------------------------------------------------------
104 * Miscellaneous configuration options
107 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
108 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
114 #define CONFIG_BOOTP_SUBNETMASK
115 #define CONFIG_BOOTP_GATEWAY
116 #define CONFIG_BOOTP_HOSTNAME
117 #define CONFIG_BOOTP_BOOTPATH
118 #define CONFIG_BOOTP_BOOTFILESIZE
122 * Command line configuration.
124 #include <config_cmd_default.h>
126 #define CONFIG_CMD_EEPROM
127 #define CONFIG_CMD_PCI
128 #define CONFIG_CMD_PCMCIA
129 #define CONFIG_CMD_DATE
130 #define CONFIG_CMD_IDE
133 #define CONFIG_DOS_PARTITION
136 * Miscellaneous configurable options
138 #define CONFIG_SYS_LONGHELP /* undef to save memory */
139 #if defined(CONFIG_CMD_KGDB)
140 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
142 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
144 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
145 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
146 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
148 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
149 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
151 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
153 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
155 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
157 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
159 #define CONFIG_SYS_ALLOC_DPRAM
161 #undef CONFIG_WATCHDOG /* watchdog disabled */
165 #define CONFIG_RTC_DS12887
167 #define RTC_BASE_ADDR 0xF5000000
168 #define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
169 #define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
171 #define CONFIG_MISC_INIT_R
174 * For booting Linux, the board info and command line data
175 * have to be in the first 8 MB of memory, since this is
176 * the maximum mapped by the Linux kernel during initialization.
178 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
180 /*-----------------------------------------------------------------------
181 * Flash configuration
184 #define CONFIG_SYS_FLASH_BASE 0xFF000000
185 #define CONFIG_SYS_FLASH_SIZE 0x00800000
187 /*-----------------------------------------------------------------------
190 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
191 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
193 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
194 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
196 #define CONFIG_FLASH_16BIT
198 /*-----------------------------------------------------------------------
199 * Hard Reset Configuration Words
201 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
202 * defines for the various registers affected by the HRCW e.g. changing
203 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
205 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
209 /* no slaves so just fill with zeros */
210 #define CONFIG_SYS_HRCW_SLAVE1 0
211 #define CONFIG_SYS_HRCW_SLAVE2 0
212 #define CONFIG_SYS_HRCW_SLAVE3 0
213 #define CONFIG_SYS_HRCW_SLAVE4 0
214 #define CONFIG_SYS_HRCW_SLAVE5 0
215 #define CONFIG_SYS_HRCW_SLAVE6 0
216 #define CONFIG_SYS_HRCW_SLAVE7 0
218 /*-----------------------------------------------------------------------
219 * Internal Memory Mapped Register
221 #define CONFIG_SYS_IMMR 0xF0000000
223 /*-----------------------------------------------------------------------
224 * Definitions for initial stack pointer and data area (in DPRAM)
226 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
227 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
228 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
229 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
231 /*-----------------------------------------------------------------------
232 * Start addresses for the final memory configuration
233 * (Set up by the startup code)
234 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
236 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
238 #define CONFIG_SYS_SDRAM_BASE 0x00000000
239 #define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
241 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
242 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
244 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
245 # define CONFIG_SYS_RAMBOOT
249 #define CONFIG_PCI_INDIRECT_BRIDGE
250 #define CONFIG_PCI_PNP
251 #define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
254 /* environment is in Flash */
255 #define CONFIG_ENV_IS_IN_FLASH 1
256 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000)
257 # define CONFIG_ENV_SIZE 0x10000
258 # define CONFIG_ENV_SECT_SIZE 0x10000
260 #define CONFIG_ENV_IS_IN_EEPROM 1
261 #define CONFIG_ENV_OFFSET 0
262 #define CONFIG_ENV_SIZE 2048
263 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
266 /*-----------------------------------------------------------------------
267 * Cache Configuration
269 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
270 #if defined(CONFIG_CMD_KGDB)
271 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
274 /*-----------------------------------------------------------------------
275 * HIDx - Hardware Implementation-dependent Registers 2-11
276 *-----------------------------------------------------------------------
277 * HID0 also contains cache control - initially enable both caches and
278 * invalidate contents, then the final state leaves only the instruction
279 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
280 * but Soft reset does not.
282 * HID1 has only read-only information - nothing to set.
284 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
285 HID0_DCI|HID0_IFEM|HID0_ABE)
286 #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
287 #define CONFIG_SYS_HID2 0
289 /*-----------------------------------------------------------------------
290 * RMR - Reset Mode Register 5-5
291 *-----------------------------------------------------------------------
292 * turn on Checkstop Reset Enable
294 #define CONFIG_SYS_RMR RMR_CSRE
296 /*-----------------------------------------------------------------------
297 * BCR - Bus Configuration 4-25
298 *-----------------------------------------------------------------------
300 #define BCR_APD01 0x10000000
301 #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
303 /*-----------------------------------------------------------------------
304 * SIUMCR - SIU Module Configuration 4-31
305 *-----------------------------------------------------------------------
307 #define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\
308 SIUMCR_CS10PC00|SIUMCR_BCTLC10)
310 /*-----------------------------------------------------------------------
311 * SYPCR - System Protection Control 4-35
312 * SYPCR can only be written once after reset!
313 *-----------------------------------------------------------------------
314 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
316 #if defined(CONFIG_WATCHDOG)
317 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
318 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
320 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
321 SYPCR_SWRI|SYPCR_SWP)
322 #endif /* CONFIG_WATCHDOG */
324 /*-----------------------------------------------------------------------
325 * TMCNTSC - Time Counter Status and Control 4-40
326 *-----------------------------------------------------------------------
327 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
328 * and enable Time Counter
330 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
332 /*-----------------------------------------------------------------------
333 * PISCR - Periodic Interrupt Status and Control 4-42
334 *-----------------------------------------------------------------------
335 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
338 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
340 /*-----------------------------------------------------------------------
341 * SCCR - System Clock Control 9-8
342 *-----------------------------------------------------------------------
343 * Ensure DFBRG is Divide by 16
345 #define CONFIG_SYS_SCCR SCCR_DFBRG01
347 /*-----------------------------------------------------------------------
348 * RCCR - RISC Controller Configuration 13-7
349 *-----------------------------------------------------------------------
351 #define CONFIG_SYS_RCCR 0
353 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
354 /*-----------------------------------------------------------------------
355 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
356 *-----------------------------------------------------------------------
358 #define CONFIG_SYS_MPTPR 0x1F00
360 /*-----------------------------------------------------------------------
361 * PSRT - Refresh Timer Register 10-16
362 *-----------------------------------------------------------------------
364 #define CONFIG_SYS_PSRT 0x0f
366 /*-----------------------------------------------------------------------
367 * PSRT - SDRAM Mode Register 10-10
368 *-----------------------------------------------------------------------
371 /* SDRAM initialization values for 8-column chips
373 #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
375 ORxS_ROWST_PBI1_A7 |\
378 #define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
379 PSDMR_SDAM_A15_IS_A5 |\
380 PSDMR_BSMA_A15_A17 |\
381 PSDMR_SDA10_PBI1_A7 |\
389 /* SDRAM initialization values for 9-column chips
391 #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
393 ORxS_ROWST_PBI1_A6 |\
396 #define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
397 PSDMR_SDAM_A16_IS_A5 |\
398 PSDMR_BSMA_A15_A17 |\
399 PSDMR_SDA10_PBI1_A6 |\
408 * Init Memory Controller:
410 * Bank Bus Machine PortSz Device
411 * ---- --- ------- ------ ------
412 * 0 60x GPCM 8 bit Boot ROM
413 * 1 60x GPCM 64 bit FLASH
414 * 2 60x SDRAM 64 bit SDRAM
418 #define CONFIG_SYS_MRS_OFFS 0x00000000
422 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
427 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
434 /* Bank 2 - 60x bus SDRAM
436 #ifndef CONFIG_SYS_RAMBOOT
437 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
442 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
444 #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
445 #endif /* CONFIG_SYS_RAMBOOT */
447 #define CONFIG_SYS_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\
452 #define CONFIG_SYS_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI)
454 /*-----------------------------------------------------------------------
456 *-----------------------------------------------------------------------
459 #define CONFIG_I82365
461 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x81000000
462 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
464 /*-----------------------------------------------------------------------
465 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
466 *-----------------------------------------------------------------------
469 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
470 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
472 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
473 #undef CONFIG_IDE_LED /* LED for ide not supported */
474 #undef CONFIG_IDE_RESET /* reset for ide not supported */
476 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
477 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
479 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
481 #define CONFIG_SYS_ATA_BASE_ADDR 0xa0000000
483 /* Offset for data I/O */
484 #define CONFIG_SYS_ATA_DATA_OFFSET 0x100
486 /* Offset for normal register accesses */
487 #define CONFIG_SYS_ATA_REG_OFFSET 0x100
489 /* Offset for alternate registers */
490 #define CONFIG_SYS_ATA_ALT_OFFSET 0x108
492 #endif /* __CONFIG_H */