include/configs/at91sam9x5ek.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2012 Atmel Corporation
   4  *
   5  * Configuation settings for the AT91SAM9X5EK board.
   6  */
   7
   8 #ifndef __CONFIG_H__
   9 #define __CONFIG_H__
  10
  11 /* ARM asynchronous clock */
  12 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  13 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000        /* 12 MHz crystal */
  14
  15 /* general purpose I/O */
  16 #define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  17
  18 /*
  19  * BOOTP options
  20  */
  21 #define CONFIG_BOOTP_BOOTFILESIZE
  22
  23 /*
  24  * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
  25  * NB: in this case, USB 1.1 devices won't be recognized.
  26  */
  27
  28 /* SDRAM */
  29 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  30 #define CONFIG_SYS_SDRAM_SIZE           0x08000000      /* 128 megs */
  31
  32 #define CONFIG_SYS_INIT_SP_ADDR \
  33         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  34
  35 /* DataFlash */
  36
  37 /* NAND flash */
  38 #ifdef CONFIG_CMD_NAND
  39 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  40 #define CONFIG_SYS_NAND_BASE            0x40000000
  41 #define CONFIG_SYS_NAND_DBW_8           1
  42 /* our ALE is AD21 */
  43 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  44 /* our CLE is AD22 */
  45 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  46 #define CONFIG_SYS_NAND_ENABLE_PIN      AT91_PIN_PD4
  47 #define CONFIG_SYS_NAND_READY_PIN       AT91_PIN_PD5
  48 #endif
  49
  50 /* USB */
  51 #ifdef CONFIG_CMD_USB
  52 #ifndef CONFIG_USB_EHCI_HCD
  53 #define CONFIG_USB_ATMEL
  54 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  55 #define CONFIG_USB_OHCI_NEW
  56 #define CONFIG_SYS_USB_OHCI_CPU_INIT
  57 #define CONFIG_SYS_USB_OHCI_REGS_BASE           ATMEL_BASE_OHCI
  58 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9x5"
  59 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      3
  60 #endif
  61 #endif
  62
  63 #ifdef CONFIG_NAND_BOOT
  64 /* bootstrap + u-boot + env + linux in nandflash */
  65 #define CONFIG_BOOTCOMMAND      "nand read " \
  66                                 "0x22000000 0x200000 0x600000; " \
  67                                 "nand read 0x21000000 0x180000 0x20000; " \
  68                                 "bootz 0x22000000 - 0x21000000"
  69 #elif defined(CONFIG_SPI_BOOT)
  70 /* bootstrap + u-boot + env + linux in spi flash */
  71 #define CONFIG_BOOTCOMMAND      "sf probe 0; " \
  72                                 "sf read 0x22000000 0x100000 0x300000; " \
  73                                 "bootm 0x22000000"
  74 #elif defined(CONFIG_SYS_USE_DATAFLASH)
  75 /* bootstrap + u-boot + env + linux in data flash */
  76 #define CONFIG_BOOTCOMMAND      "sf probe 0; " \
  77                                 "sf read 0x22000000 0x84000 0x294000; " \
  78                                 "bootm 0x22000000"
  79 #endif
  80
  81 /* SPL */
  82 #define CONFIG_SPL_MAX_SIZE             0x6000
  83 #define CONFIG_SPL_STACK                0x308000
  84
  85 #define CONFIG_SPL_BSS_START_ADDR       0x20000000
  86 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  87 #define CONFIG_SYS_SPL_MALLOC_START     0x20080000
  88 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x80000
  89
  90 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
  91
  92 #define CONFIG_SYS_MASTER_CLOCK         132096000
  93 #define CONFIG_SYS_AT91_PLLA            0x20c73f03
  94 #define CONFIG_SYS_MCKR                 0x1301
  95 #define CONFIG_SYS_MCKR_CSS             0x1302
  96
  97 #ifdef CONFIG_SD_BOOT
  98 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
  99 #endif
 100 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 101 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 102 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 103 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 104 #define CONFIG_SYS_NAND_OOBSIZE         64
 105 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
 106 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
 107
 108 #endif