1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2013 Atmel Corporation.
4 * Josh Wu <josh.wu@atmel.com>
6 * Configuation settings for the AT91SAM9N12-EK boards.
9 #ifndef __AT91SAM9N12_CONFIG_H_
10 #define __AT91SAM9N12_CONFIG_H_
12 /* ARM asynchronous clock */
13 #define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
14 #define CFG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
16 /* Misc CPU related */
17 #define CFG_SYS_SDRAM_BASE 0x20000000
18 #define CFG_SYS_SDRAM_SIZE 0x08000000
23 #ifdef CONFIG_CMD_NAND
24 #define CFG_SYS_NAND_BASE 0x40000000
25 #define CFG_SYS_NAND_MASK_ALE (1 << 21)
26 #define CFG_SYS_NAND_MASK_CLE (1 << 22)
27 #define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
28 #define CFG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
31 #define CONFIG_EXTRA_ENV_SETTINGS \
32 "console=console=ttyS0,115200\0" \
33 "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
34 "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
38 #define CFG_SYS_MASTER_CLOCK 132096000
39 #define CFG_SYS_AT91_PLLA 0x20953f03
40 #define CFG_SYS_MCKR 0x1301
41 #define CFG_SYS_MCKR_CSS 0x1302