1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
13 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
15 /* ARM asynchronous clock */
16 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
17 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
19 #define CONFIG_AT91SAM9M10G45EK
21 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
22 #define CONFIG_SETUP_MEMORY_TAGS
23 #define CONFIG_INITRD_TAG
25 /* general purpose I/O */
26 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
29 #define LCD_BPP LCD_COLOR8
30 #define CONFIG_LCD_LOGO
31 #undef LCD_TEST_PATTERN
32 #define CONFIG_LCD_INFO
33 #define CONFIG_LCD_INFO_BELOW_LOGO
34 #define CONFIG_ATMEL_LCD
35 #define CONFIG_ATMEL_LCD_RGB565
36 /* board specific(not enough SRAM) */
37 #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
42 #define CONFIG_BOOTP_BOOTFILESIZE
45 #define CONFIG_SYS_SDRAM_BASE 0x70000000
46 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
48 #define CONFIG_SYS_INIT_SP_ADDR \
49 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
52 #ifdef CONFIG_CMD_NAND
53 #define CONFIG_SYS_MAX_NAND_DEVICE 1
54 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
55 #define CONFIG_SYS_NAND_DBW_8
57 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
59 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
60 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
61 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
66 #define CONFIG_RESET_PHY_R
67 #define CONFIG_AT91_WANTS_COMMON_PHY
69 #ifdef CONFIG_NAND_BOOT
70 /* bootstrap + u-boot + env in nandflash */
72 #define CONFIG_BOOTCOMMAND \
73 "nand read 0x70000000 0x200000 0x300000;" \
76 /* bootstrap + u-boot + env + linux in mmc */
78 #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \
79 "fatload mmc 0:1 0x72000000 zImage; " \
80 "bootz 0x72000000 - 0x71000000"
84 * Size of malloc() pool
86 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
89 #define CONFIG_SPL_MAX_SIZE 0x010000
90 #define CONFIG_SPL_STACK 0x310000
92 #define CONFIG_SYS_MONITOR_LEN 0x80000
96 #define CONFIG_SPL_BSS_START_ADDR 0x70000000
97 #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
98 #define CONFIG_SYS_SPL_MALLOC_START 0x70080000
99 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
101 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
103 #elif CONFIG_NAND_BOOT
104 #define CONFIG_SPL_NAND_SOFTECC
105 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
106 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
107 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
109 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
110 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
111 #define CONFIG_SYS_NAND_PAGE_COUNT 64
112 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
113 #define CONFIG_SYS_NAND_ECCSIZE 256
114 #define CONFIG_SYS_NAND_ECCBYTES 3
115 #define CONFIG_SYS_NAND_OOBSIZE 64
116 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
117 48, 49, 50, 51, 52, 53, 54, 55, \
118 56, 57, 58, 59, 60, 61, 62, 63, }
121 #define CONFIG_SPL_ATMEL_SIZE
122 #define CONFIG_SYS_MASTER_CLOCK 132096000
123 #define CONFIG_SYS_AT91_PLLA 0x20c73f03
124 #define CONFIG_SYS_MCKR 0x1301
125 #define CONFIG_SYS_MCKR_CSS 0x1302