1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
13 /* ARM asynchronous clock */
14 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
15 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
17 /* general purpose I/O */
20 #define LCD_BPP LCD_COLOR8
23 #define CONFIG_SYS_SDRAM_BASE 0x70000000
24 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
26 #define CONFIG_SYS_INIT_SP_ADDR \
27 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
30 #ifdef CONFIG_CMD_NAND
31 #define CONFIG_SYS_MAX_NAND_DEVICE 1
32 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
33 #define CONFIG_SYS_NAND_DBW_8
35 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
37 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
38 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
39 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
43 #ifdef CONFIG_NAND_BOOT
44 /* bootstrap + u-boot + env in nandflash */
46 /* bootstrap + u-boot + env + linux in mmc */
50 #define CONFIG_SPL_MAX_SIZE 0x010000
51 #define CONFIG_SPL_STACK 0x310000
53 #define CONFIG_SYS_MONITOR_LEN 0x80000
57 #define CONFIG_SPL_BSS_START_ADDR 0x70000000
58 #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
59 #define CONFIG_SYS_SPL_MALLOC_START 0x70080000
60 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
62 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
64 #elif CONFIG_NAND_BOOT
65 #define CONFIG_SPL_NAND_SOFTECC
66 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
68 #define CONFIG_SYS_NAND_ECCSIZE 256
69 #define CONFIG_SYS_NAND_ECCBYTES 3
70 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
71 48, 49, 50, 51, 52, 53, 54, 55, \
72 56, 57, 58, 59, 60, 61, 62, 63, }
75 #define CONFIG_SYS_MASTER_CLOCK 132096000
76 #define CONFIG_SYS_AT91_PLLA 0x20c73f03
77 #define CONFIG_SYS_MCKR 0x1301
78 #define CONFIG_SYS_MCKR_CSS 0x1302