include/configs/at91sam9263ek.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * Configuation settings for the AT91SAM9263EK board.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_AT91_LEGACY
  31
  32 /* ARM asynchronous clock */
  33 #define AT91_MAIN_CLOCK         16367660        /* 16.367 MHz crystal */
  34 #define CONFIG_SYS_HZ           1000
  35
  36 #define CONFIG_ARM926EJS        1       /* This is an ARM926EJS Core    */
  37 #define CONFIG_AT91SAM9263      1       /* It's an Atmel AT91SAM9263 SoC*/
  38 #define CONFIG_AT91SAM9263EK    1       /* on an AT91SAM9263EK Board    */
  39 #define CONFIG_ARCH_CPU_INIT
  40 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff  */
  41
  42 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs      */
  43 #define CONFIG_SETUP_MEMORY_TAGS 1
  44 #define CONFIG_INITRD_TAG       1
  45
  46 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
  47 #define CONFIG_SKIP_LOWLEVEL_INIT
  48 #define CONFIG_SKIP_RELOCATE_UBOOT
  49 #endif
  50
  51 /*
  52  * Hardware drivers
  53  */
  54 #define CONFIG_ATMEL_USART      1
  55 #undef CONFIG_USART0
  56 #undef CONFIG_USART1
  57 #undef CONFIG_USART2
  58 #define CONFIG_USART3           1       /* USART 3 is DBGU */
  59
  60 /* LCD */
  61 #define CONFIG_LCD                      1
  62 #define LCD_BPP                         LCD_COLOR8
  63 #define CONFIG_LCD_LOGO                 1
  64 #undef LCD_TEST_PATTERN
  65 #define CONFIG_LCD_INFO                 1
  66 #define CONFIG_LCD_INFO_BELOW_LOGO      1
  67 #define CONFIG_SYS_WHITE_ON_BLACK               1
  68 #define CONFIG_ATMEL_LCD                1
  69 #define CONFIG_ATMEL_LCD_BGR555         1
  70 #define CONFIG_SYS_CONSOLE_IS_IN_ENV            1
  71
  72 /* LED */
  73 #define CONFIG_AT91_LED
  74 #define CONFIG_RED_LED          AT91_PIN_PB7    /* this is the power led */
  75 #define CONFIG_GREEN_LED        AT91_PIN_PB8    /* this is the user1 led */
  76 #define CONFIG_YELLOW_LED       AT91_PIN_PC29   /* this is the user2 led */
  77
  78 #define CONFIG_BOOTDELAY        3
  79
  80 /*
  81  * BOOTP options
  82  */
  83 #define CONFIG_BOOTP_BOOTFILESIZE       1
  84 #define CONFIG_BOOTP_BOOTPATH           1
  85 #define CONFIG_BOOTP_GATEWAY            1
  86 #define CONFIG_BOOTP_HOSTNAME           1
  87
  88 /*
  89  * Command line configuration.
  90  */
  91 #include <config_cmd_default.h>
  92 #undef CONFIG_CMD_BDI
  93 #undef CONFIG_CMD_FPGA
  94 #undef CONFIG_CMD_IMI
  95 #undef CONFIG_CMD_IMLS
  96 #undef CONFIG_CMD_LOADS
  97 #undef CONFIG_CMD_SOURCE
  98
  99 #define CONFIG_CMD_PING         1
 100 #define CONFIG_CMD_DHCP         1
 101 #define CONFIG_CMD_NAND         1
 102 #define CONFIG_CMD_USB          1
 103
 104 /* SDRAM */
 105 #define CONFIG_NR_DRAM_BANKS            1
 106 #define PHYS_SDRAM                      0x20000000
 107 #define PHYS_SDRAM_SIZE                 0x04000000      /* 64 megs */
 108
 109 /* DataFlash */
 110 #define CONFIG_ATMEL_DATAFLASH_SPI
 111 #define CONFIG_HAS_DATAFLASH            1
 112 #define CONFIG_SYS_SPI_WRITE_TOUT               (5*CONFIG_SYS_HZ)
 113 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
 114 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
 115 #define AT91_SPI_CLK                    15000000
 116 #define DATAFLASH_TCSS                  (0x1a << 16)
 117 #define DATAFLASH_TCHS                  (0x1 << 24)
 118
 119 /* NOR flash, if populated */
 120 #ifdef CONFIG_SYS_USE_NORFLASH
 121 #define CONFIG_SYS_FLASH_CFI                    1
 122 #define CONFIG_FLASH_CFI_DRIVER                 1
 123 #define PHYS_FLASH_1                            0x10000000
 124 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 125 #define CONFIG_SYS_MAX_FLASH_SECT               256
 126 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 127
 128 #define CONFIG_SYS_MONITOR_SEC  1:0-3
 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 130 #define CONFIG_SYS_MONITOR_LEN  (256 << 10)
 131 #define CONFIG_ENV_IS_IN_FLASH  1
 132 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x007FE000)
 133 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
 134
 135 /* Address and size of Primary Environment Sector */
 136 #define CONFIG_ENV_SIZE         0x2000
 137
 138 #define xstr(s)   str(s)
 139 #define str(s)  #s
 140
 141 #define CONFIG_EXTRA_ENV_SETTINGS       \
 142         "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
 143         "update=" \
 144                 "protect off ${monitor_base} +${filesize};" \
 145                 "erase ${monitor_base} +${filesize};" \
 146                 "cp.b ${load_addr} ${monitor_base} ${filesize};" \
 147                 "protect on ${monitor_base} +${filesize}\0"
 148
 149 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 150 #define MASTER_PLL_MUL          171
 151 #define MASTER_PLL_DIV          14
 152
 153 /* clocks */
 154 #define CONFIG_SYS_MOR_VAL                                              \
 155                 (AT91_PMC_MOSCEN |                                      \
 156                  (255 << 8))            /* Main Oscillator Start-up Time */
 157 #define CONFIG_SYS_PLLAR_VAL                                            \
 158                 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
 159                  AT91_PMC_OUT |                                         \
 160                  AT91_PMC_PLLCOUNT |    /* PLL Counter */               \
 161                  (2 << 28) |            /* PLL Clock Frequency Range */ \
 162                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
 163
 164 /* PCK/2 = MCK Master Clock from PLLA */
 165 #define CONFIG_SYS_MCKR1_VAL            \
 166                 (AT91_PMC_CSS_SLOW |    \
 167                  AT91_PMC_PRES_1 |      \
 168                  AT91SAM9_PMC_MDIV_2 |  \
 169                  AT91_PMC_PDIV_1)
 170 /* PCK/2 = MCK Master Clock from PLLA */
 171 #define CONFIG_SYS_MCKR2_VAL            \
 172                 (AT91_PMC_CSS_PLLA |    \
 173                  AT91_PMC_PRES_1 |      \
 174                  AT91SAM9_PMC_MDIV_2 |  \
 175                  AT91_PMC_PDIV_1)
 176
 177 /* define PDC[31:16] as DATA[31:16] */
 178 #define CONFIG_SYS_PIOD_PDR_VAL1        0xFFFF0000
 179 /* no pull-up for D[31:16] */
 180 #define CONFIG_SYS_PIOD_PPUDR_VAL       0xFFFF0000
 181 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
 182 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL                                   \
 183         (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |     \
 184          AT91_MATRIX_EBI0_CS1A_SDRAMC)
 185
 186 /* SDRAM */
 187 /* SDRAMC_MR Mode register */
 188 #define CONFIG_SYS_SDRC_MR_VAL1         0
 189 /* SDRAMC_TR - Refresh Timer register */
 190 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
 191 /* SDRAMC_CR - Configuration register*/
 192 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
 193                 (AT91_SDRAMC_NC_9 |                                             \
 194                  AT91_SDRAMC_NR_13 |                                            \
 195                  AT91_SDRAMC_NB_4 |                                             \
 196                  AT91_SDRAMC_CAS_3 |                                            \
 197                  AT91_SDRAMC_DBW_32 |                                           \
 198                  (1 <<  8) |            /* Write Recovery Delay */              \
 199                  (7 << 12) |            /* Row Cycle Delay */                   \
 200                  (2 << 16) |            /* Row Precharge Delay */               \
 201                  (2 << 20) |            /* Row to Column Delay */               \
 202                  (5 << 24) |            /* Active to Precharge Delay */         \
 203                  (1 << 28))             /* Exit Self Refresh to Active Delay */
 204
 205 /* Memory Device Register -> SDRAM */
 206 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
 207 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
 208 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
 209 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
 210 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
 211 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
 212 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
 213 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
 214 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
 215 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
 216 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
 217 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
 218 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
 219 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
 220 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
 221 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
 222 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
 223 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
 224
 225 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 226 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
 227                 (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |   \
 228                  AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
 229 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
 230                 (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |   \
 231                  AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
 232 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 233                 (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
 234 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 235                 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |       \
 236                  AT91_SMC_DBW_16 |                              \
 237                  AT91_SMC_TDFMODE |                             \
 238                  AT91_SMC_TDF_(6))
 239
 240 /* user reset enable */
 241 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 242                 (AT91_RSTC_KEY |                \
 243                 AT91_RSTC_PROCRST |             \
 244                 AT91_RSTC_RSTTYP_WAKEUP |       \
 245                 AT91_RSTC_RSTTYP_WATCHDOG)
 246
 247 /* Disable Watchdog */
 248 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 249                 (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |       \
 250                  AT91_WDT_WDV |                                 \
 251                  AT91_WDT_WDDIS |                               \
 252                  AT91_WDT_WDD)
 253 #endif
 254
 255 #else
 256 #define CONFIG_SYS_NO_FLASH                     1
 257 #endif
 258
 259 /* NAND flash */
 260 #ifdef CONFIG_CMD_NAND
 261 #define CONFIG_NAND_ATMEL
 262 #define CONFIG_SYS_MAX_NAND_DEVICE              1
 263 #define CONFIG_SYS_NAND_BASE                    0x40000000
 264 #define CONFIG_SYS_NAND_DBW_8                   1
 265 /* our ALE is AD21 */
 266 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
 267 /* our CLE is AD22 */
 268 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
 269 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PD15
 270 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PA22
 271
 272 #endif
 273
 274 /* Ethernet */
 275 #define CONFIG_MACB                     1
 276 #define CONFIG_RMII                     1
 277 #define CONFIG_NET_MULTI                1
 278 #define CONFIG_NET_RETRY_COUNT          20
 279 #define CONFIG_RESET_PHY_R              1
 280
 281 /* USB */
 282 #define CONFIG_USB_ATMEL
 283 #define CONFIG_USB_OHCI_NEW             1
 284 #define CONFIG_DOS_PARTITION            1
 285 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 286 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00a00000      /* AT91SAM9263_UHP_BASE */
 287 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9263"
 288 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 289 #define CONFIG_USB_STORAGE              1
 290 #define CONFIG_CMD_FAT                  1
 291
 292 #define CONFIG_SYS_LOAD_ADDR                    0x22000000      /* load address */
 293
 294 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
 295 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
 296
 297 #ifdef CONFIG_SYS_USE_DATAFLASH
 298
 299 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 300 #define CONFIG_ENV_IS_IN_DATAFLASH      1
 301 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 302 #define CONFIG_ENV_OFFSET               0x4200
 303 #define CONFIG_ENV_ADDR         (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 304 #define CONFIG_ENV_SIZE         0x4200
 305 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
 306 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 307                                 "root=/dev/mtdblock0 " \
 308                                 "mtdparts=atmel_nand:-(root) "\
 309                                 "rw rootfstype=jffs2"
 310
 311 #elif CONFIG_SYS_USE_NANDFLASH
 312
 313 /* bootstrap + u-boot + env + linux in nandflash */
 314 #define CONFIG_ENV_IS_IN_NAND   1
 315 #define CONFIG_ENV_OFFSET               0x60000
 316 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 317 #define CONFIG_ENV_SIZE         0x20000         /* 1 sector = 128 kB */
 318 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
 319 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 320                                 "root=/dev/mtdblock5 " \
 321                                 "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
 322                                 "rw rootfstype=jffs2"
 323
 324 #endif
 325
 326 #define CONFIG_BAUDRATE         115200
 327 #define CONFIG_SYS_BAUDRATE_TABLE       {115200 , 19200, 38400, 57600, 9600 }
 328
 329 #define CONFIG_SYS_PROMPT               "U-Boot> "
 330 #define CONFIG_SYS_CBSIZE               256
 331 #define CONFIG_SYS_MAXARGS              16
 332 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 333 #define CONFIG_SYS_LONGHELP             1
 334 #define CONFIG_CMDLINE_EDITING  1
 335 #define CONFIG_AUTO_COMPLETE
 336 #define CONFIG_SYS_HUSH_PARSER
 337 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 338
 339 /*
 340  * Size of malloc() pool
 341  */
 342 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
 343 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* 128 bytes for initial data */
 344
 345 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
 346
 347 #ifdef CONFIG_USE_IRQ
 348 #error CONFIG_USE_IRQ not supported
 349 #endif
 350
 351 #endif